ISL6211 Datasheet, PDF (11/16 Pages) Intersil Corporation – Crusoe™ Processor Core-Voltage Regulator

ISL6211
is usually higher compared to the load level at which
transition into hysteretic mode had occurred.
The hysteretic mode of operation can be disabled by the
FCCM pin when it is set low. The presence of this pin
enhances applicability of the controller.
The Figure 10 shows the example of an application circuit
where the hysteretic mode of operation is only allowed in a
Deep Sleep Extension (DSX) mode. In this mode the CPU
has stopped and its current is significantly lower compared
to other modes of operation. Using the FCCM pin simplifies
control of converter modes of operation and increases the
efficiency.
R1
Q1
START
R2
Q2
DSX
6 _ALTV
ISL6211
5 _FCCM
FIGURE 10. CONFIGURATION FOR HYSTERETIC
OPERATION IN DSX MODE ONLY
the origin, has a zero-pole pair that causes a flat gain region
at frequencies between the zero and the pole.
F_Z
=
--------------¹----------------
2π ⋅ R₂ ⋅ C₁
=
6kHz
F_P
=
--------------¹----------------
2π ⋅ R₁ ⋅ C₂
=
600 k H z
This region is also associated with phase ‘bump’ or reduced
phase shift. The amount of phase shift reduction depends on
how wide the region of flat gain is and has a maximum value
of 90 degrees. To further simplify the converter
compensation, the modulator gain is kept independent of the
input voltage variation by providing feed-forward of V_IN to the
oscillator ramp.
CONVERTER
C2
R2 ^C1
R1
EA
G_EA=18dB
MODULATOR
F_PO
TYPE 2 EA
G_EA=14dB
F_Z
F_P
F_C
Gate Control Logic
The gate control logic translates generated PWM signals
into gate drive signals providing necessary amplification,
level shift and shoot-through protection. It helps optimize the
IC performance over a wide range of the operational
conditions. As MOSFET switching time can very dramatically
from type to type and with input voltage, the gate control
logic provides adaptive dead time by monitoring the actual
gate voltages of both the upper and the lower MOSFETs.
Feedback Loop Compensation
Due to the implemented current mode control, the modulator
has a single pole response with -1 slope at frequency
determined by load ,
F_PO
=
----------------¹----------------
2π ⋅ R_O ⋅ C_O
where Ro is load resistance, Co is load capacitance. For this
type of modulator Type 2 compensation circuit is usually
sufficient. To reduce number of external components and
remove the burden of determining compensation
components from the system designer, the PWM controller
has an internally compensated error amplifier.
The Figure 11 shows a Type 2 amplifier and its response
along with the responses of a current mode modulator and of
the converter. The Type 2 amplifier, in addition to the pole at
FIGURE 11.
The zero frequency, the amplifier high-frequency gain and
the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within the 10kHz...50kHz range gives
some additional phase ‘boost’.
Protections
The converter output is monitored and protected against
extreme overload, short circuit, over-voltage and under-
voltage conditions.
A sustained overload on the output sets the PGOOD pin low
and latches-off the whole chip. The controller operation can
be restored by cycling the VCC voltage or enable (EN) pin.
11