X40430_06 Datasheet, PDF (8/26 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430, X40431, X40434, X40435
Figure 2. Two Uses of Multiple Voltage Monitoring
V_CC
X40431-A
6-10V
5V
V_CC RESET
1M
3.3V
390K
V2MON ^V2FAIL
V3MON
(1.7V) _V3FAIL
System
Reset
Power
Fail
Interrupt
Notice: No external components required to monitor three voltages.
Unreg.
Supply
Figure 3. V_TRIPX Set/Reset Conditions
V_TRIPX
(X = 1, 2, 3)
V_CC/V2MON/V3MON
5V
Reg
3.0V
Reg
1.8V
Reg
V_CC
X40431-B
V_CC
RESET
V2MON
V2FAIL
V3MON
V3FAIL
V_P
WDO
SCL
0
70
70
7
System
Reset
SDA
A0h
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
WDO signal going active. A minimum sequence to
reset the watchdog timer requires four microprocessor
instructions namely, a Start, Clock Low, Clock High
and Stop. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer
period. The microprocessor can change these watch-
dog bits by writing to the X40430, X40431, X40434,
X40435 control register (also refer to page 20).
8
00h
t_WC
Figure 4. Watchdog Restart
.6µs
1.3µs
SCL
SDA
Start
WDT Reset ^Stop
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE (OPTIONAL)
The X40430 is shipped with standard V1, V2 and V3
threshold (V_TRIP1, V_TRIP2, V_TRIP3) voltages. These
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X40430,
X40431, X40434, X40435 trip points may be adjusted.
The procedure is described in the following situation,
and uses the application of a high voltage control sig-
nal.
FN8251.1
May 24, 2006