X40430_06 Datasheet, PDF (2/26 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

BLOCK DIAGRAM
X40430, X40431, X40434, X40435
V3MON
V2MON
+
V3 Monitor
Logic
-
V2 Monitor
Logic
V_TRIP3
V_CC or
V2MON*
+
V_TRIP2
-
SDA
Data
Register
WP
Command
Decode Test
& Control
SCL
Logic
Fault Detection
Register
Status
Register
EEPROM
Array
V_CC
(V1MON)
*X40430, X40431=V2MON
X40434, X40435 =V_CC
V_CC Monitor
Logic
+
V_TRIP1
-
Watchdog
and
Reset Logic
Power-on,
Manual Reset
Low Voltage
Reset
Generation
V3FAIL
V2FAIL
WDO
MR
RESET
X40430/34
RESET
X40431/35
LOWLINE
Device
Expected System
Voltages
Vtrip1(V)
X40430, X40431
-A
5V; 3V or 3.3V; 1.8V
-B
5V; 3V; 1.8V
-C
3.3V; 2.5V; 1.8V
2.0–4.75*
4.55–4.65*
4.35–4.45*
2.95–3.05*
X40434, X40435
-A
5V; 3.3V; 1.5V
-B
5V; 3V or 3.3V; 1.5V
-C
5V; 3 or 3.3V; 1.2V
2.0–4.75*
4.55–4.65*
4.55–4.65*
4.55–4.65*
*Voltage monitor requires Vcc to operate. Others are independent of Vcc.
Vtrip2(V)
1.70–4.75
2.85–2.95
2.55–2.65
2.15–2.25
0.90–3.50*
1.25–1.35*
1.25–1.35*
0.95–1.05*
Vtrip3(V)
1.70–4.75
1.65–1.75
1.65–1.75
1.65–1.75
1.70–4.75
3.05–3.15
2.85–2.95
2.85–2.95
POR
(system)
RESET = X40430
RESET = X40431
RESET = X40434
RESET = X40435
2
FN8251.1
May 24, 2006