X40430_06 Datasheet, PDF (17/26 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430, X40431, X40434, X40435
Figure 16. Random Address Read Sequence
S
Signals from ^t
Slave
the Master
a
r
Address
Byte
Address
S
t
Slave
a _Address
r
S
t
o
t
t
p
SDA Bus
101 00 0
1
Signals from
the Slave
A
A
C
C
K
K
A
C
K
Data
Figure 17. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
Slave
t
Address
o
A
A
A
p
C
C
C
K
K
K
1
A
C
K
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
17
FN8251.1
May 24, 2006