X40430_06 Datasheet, PDF (11/26 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430, X40431, X40434, X40435
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
BP: Block Protect Bits (Nonvolatile)
The Block Protect Bit BP, determines which blocks of
the array are write protected. A write to a protected
block of memory is ignored. The block protect bit will
prevent write operations to half or none of the array.
Protected Addresses
BP
(Size)
0
None
1 100h – 1FFh (256 bytes)
Memory Array
Lock
None
Upper Half of
Memory Array
PUP1, PUP0: Power-up Bits (Nonvolatile)
The Power-up bits, PUP1 and PUP0, determine the
t_PURST time delay. The nominal power-up times are
shown in the following table.
PUP1
0
0
1
1
PUP0
0
1
0
1
Power-on Reset Delay (t_PURST)
50ms
200ms (factory setting)
400ms
800ms
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1
0
0
1
1
WD0
0
1
0
1
Watchdog Time Out Period
1.4 seconds
200 milliseconds
25 milliseconds
disabled (factory setting)
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceded by a start and ended with a stop).
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
– Write one byte value to the Control Register that has
all the control bits set to the desired state. The Control
register can be represented as qxys 001r in binary,
where xy are the WD bits, s is the BP bit and qr are the
power-up bits. This operation proceeded by a start and
ended with a stop bit. Since this is a nonvolatile write
cycle it will take up to 10ms (max.) to complete. The
RWEL bit is reset by this cycle and the sequence must
be repeated to change the nonvolatile bits again. If bit
2 is set to ‘1’ in this third step (qxys 011r) then the
RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and
BP bits remain unchanged. Writing a second byte to
the control register is not allowed. Doing so aborts the
write operation and returns a NACK.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
Notes: 1. t_PURST is set to 200ms as factory default.
2. Watch Dog Timer bits are shipped disabled.
FAULT DETECTION REGISTER
The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
Low Voltage Fail bits are volatile
7
6
5
4
3
2 10
LV1F LV2F LV3F WDF MRF 0 0 0
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
There is no need to set the WEL or RWEL in the
control register to access this FDR.
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FN8251.1
May 24, 2006