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X40430_06 Datasheet, PDF (1/26 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor | |||
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X40430, X40431, X40434, X40435
®
4Kbit EEPROM
Data Sheet
May 24, 2006
FN8251.1
Triple Voltage Monitor with Integrated
CPU Supervisor
FEATURES
⢠Monitoring voltages: 5V to 9V
⢠Independent core voltage monitor
⢠Triple voltage detection and reset assertion
âStandard reset threshold settings. See selec-
tion table on page 2.
âAdjust low voltage reset threshold voltages
using special programming sequence
âReset signal valid to VCC = 1V
âMonitor three separate voltages
⢠Fault detection register
⢠Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
⢠Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
⢠Debounced manual reset input
⢠Low power CMOS
â25µA typical standby current, watchdog on
â6µA typical standby current, watchdog off
⢠Memory security
⢠4Kbits of EEPROM
â16 byte page write mode
â5ms write cycle time (typical)
⢠Built-in inadvertent write protection
âPower-up/power-down protection circuitry
âBlock lock protect 0, or 1/2, of EEPROM
⢠400kHz 2-wire interface
⢠2.7V to 5.5V power supply operation
⢠Available packages
â14 Ld SOIC, TSSOP
⢠Pb-free plus anneal available (RoHS compliant)
APPLICATIONS
⢠Communication equipment
âRouters, hubs, switches
âDisk arrays, network storage
⢠Industrial systems
âProcess control
âIntelligent instrumentation
⢠Computer systems
â Computers
âNetwork servers
DESCRIPTION
The X40430, X40431, X40434, X40435 combines
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision,
manual reset, and Block Lock⢠protect serial EEPROM
in one package. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
Low VCC detection circuitry protects the userâs system
from low voltage conditions, resetting the system
when VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second and third volt-
age monitor circuit tracks the unregulated supply to
provide a power fail warning or monitors different
power supply voltage. Three common low voltage
combinations are available. However, Intersilâs unique
circuits allows the threshold for either voltage monitor
to be reprogrammed to meet specific system level
requirements or to fine-tune the threshold for applica-
tions requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersilâs Block Lock protection.
The array is internally organized as x 8. The device
features a 2-wire interface and software protocol
allowing operation on an I2C bus.
The device utilizes Intersilâs proprietary Direct Writeâ¢
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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