X40430_06 Datasheet, PDF (16/26 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430, X40431, X40434, X40435
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF_hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF_hex
General Purpose Memory Organization, A8:A0
Address: 000h to 1FFh
General Purpose Memory Array Configuration
Memory Address
A8:A0
000h
0FFh
100h
1FFh
Lower 256 bytes
Upper 256 bytes
Block Protect Option
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x = 0 is for Array, x = 1 is for Control Register or
Fault Detection Register.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 14. X40430, X40431, X40434, X40435
Addressing
Slave Byte
General Purpose Memory _{1 0 1 0 0 0 A8 R/W}
Control Register
1 0 1 1 0 0 1 R/W
Fault Detection Register 1 0 1 1 0 0 0 R/W
Word Address
General Purpose Memory _{A7 A6 A5 A4 A3 A2 A1 A0}
Control Register
111 11111
Fault Detection Register 1 1 1 1 1 1 1 1
– last bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for t_PURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
Figure 15. Current Address Read Sequence
.
S
Signals from
the Master
t
a
r
Slave
Address
S
t
o
t
p
SDA Bus
10 1000 1
Signals from
the Slave
A
C
K
Data
16
FN8251.1
May 24, 2006