X40430_06 Datasheet, PDF (21/26 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430, X40431, X40434, X40435
TIMING DIAGRAMS
Bus Timing
t_F
t_HIGH
SCL
t_SU:STA
SDA IN
t_HD:STA
t_SU:DAT
t_LOW
t_HD:DAT
SDA OUT
t_R
t_AA t_DH
t_SU:STO
t_BUF
WP Pin Timing
SCL
START
SDA IN
WP
t_SU:WP
Clk 1
Slave Address Byte
Clk 9
t_HD:WP
Write Cycle Timing
SCL
SDA
8^th Bit of Last Byte
ACK
t_WC
Stop
Condition
Start
Condition
Nonvolatile Write Cycle Timing
Symbol
t_WC(1)
Parameter
Write Cycle Time
Min
Typ
Max
Unit
5
10
ms
Note: (1) t_WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
21
FN8251.1
May 24, 2006