ISL267450_14 Datasheet, PDF (8/19 Pages) Intersil Corporation – 12-Bit, 1MSPS SAR ADCs

ISL267450
Electrical Specifications Limits established by characterization and are not production tested. V_DD = +3.0V to +3.3V, F_SCLK = 15MHz,
F_S = 833kSPS, V_REF = 1.25V, F_IN = 200kHz; V_REF = 2.5V; V_CM = V_REF, T_A = T_MIN to T_MAX unless otherwise noted. Typical values are at T_A = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
t_QUIET Quiet Time Before Sample
25
ns
t_CSS
CS Falling Edge to S_CLK Falling Edge Setup Time
10
ns
t_DISABLE CS Falling Edge to SDATA Disable Time (Note 9) Extrapolated back to true bus relinquish
10
35
µs
t_SWH SCLK High Pulsewidth
0.4 x t_SCLK
0.6 x t_SCLK ns
t_SWL SCLK Low Pulsewidth
0.4 x t_SCLK
0.6 x t_SCLK ns
t_CLKDV SCLK Falling Edge to SDATA Valid
40
ns
t_SDH
SCLK Falling Edge to SDATA Hold
10
ns
t_ACQ
Acquisition Time (Note 8)
ns
t_CSW CS Pulse Width
10
ns
t_CDV
CS Falling Edge to SDATA Valid
20
ns
NOTE:
9. During characterization, t_DISABLE is measured from the release point with a 10pF load (see Figure 2 on page 8) and the equivalent timing using the
AD7450 loading (50pF) is calculated.
FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM
VDD
RL
2.85k
OUTPUT
PIN
CL
10 pF
FIGURE 2. EQUIVALENT LOAD CIRCUIT
8
FN8341.0
August 10, 2012