ISL267450_14 Datasheet, PDF (16/19 Pages) Intersil Corporation – 12-Bit, 1MSPS SAR ADCs

ISL267450
The ISL267450 is tested using the CCIF standard, where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is as
per the THD specification, where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 0.1dB or 3dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
a 200mV_P-P sine wave applied to the common-mode voltage of
V_IN+ and V_IN– of frequency fs as shown by Equation 3.:
CMRR(dB) = 10log(Pfl ⁄ Pfs)
(EQ. 3)
Pf is the power at the frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero-Code Error
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal V_IN+ – V_IN– (i.e., 0 LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal V_IN+ – V_IN– (i.e., +V_REF – 1 LSB), after
the zero code error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal V_IN+ – VIN– (i.e., -V_REF + 1 LSB), after
the zero code error has been adjusted out.
Track and Hold Acquisition Time
The track and hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the applied
input signal.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to ADC V_DD
supply of frequency f_S. The frequency of this input varies from
1kHz to 1MHz.
PSRR(dB) = 10log (Pf ⁄ Pfs)
(EQ. 4)
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency f_s in the ADC output.
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16
FN8341.0
August 10, 2012