ISL267450_14 Datasheet, PDF (7/19 Pages) Intersil Corporation – 12-Bit, 1MSPS SAR ADCs

ISL267450
Electrical Specifications V_DD = +3.0V to +3.3V, F_SCLK = 15MHz, F_S = 833kSPS, V_REF = 1.25V, F_IN = 200kHz; V_DD = +4.75V to
+5.25V, F_SCLK = 18MHz, F_S = 1MSPS, V_REF = 2.5V, F_IN = 300kHz; V_CM = V_REF, T_A = T_MIN to T_MAX unless otherwise noted. Typical values are at
T_A = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 6)
TYP
(Note 6)
UNITS
I_DD
Positive Supply Input Current
Static
V_DD = 3V/5V; SCLK ON or OFF
Dynamic
V_DD = 5V; f_S = 1MSPS
V_DD = 3V; f_S = 833kSPS
P_D
Power Dissipation
Static Mode
V_DD = 3V/5V; SCLK ON or OFF
Dynamic
V_DD = 5V; f_S = 1MSPS
V_DD = 3V; f_S = 833kSPS
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The absolute voltage applied to each analog input must not exceed V_DD.
8. Read about “Acquisition Time” on page 14 for a discussion of this parameter.
1
µA
1.7
mA
1.25
mA
5
µW
8.5
mW
3.75
mW
Electrical Specifications Limits established by characterization and are not production tested. V_DD = +4.75V to +5.25V,
F_SCLK = 18MHz, F_S = 1MSPS, V_REF = 2.5V, F_IN = 300kHz; V_CM = V_REF, T_A = T_MIN to T_MAX unless otherwise noted. Typical values are at T_A = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
fSCLK
t_SCLK
t_CONVERT
t_QUIET
t_CSS
t_DISABLE
Clock Frequency
Clock Period
Conversion Time
Quiet Time Before Sample
16 x t_SCLK
CS Falling Edge to S_CLK Falling Edge Setup Time
CS Falling Edge to SDATA Disable Time (Note 9) Extrapolated back to true bus relinquish
Data Access Time after SCLK Falling Edge
0.05
55
25
10
10
18
MHz
ns
888
ns
ns
ns
35
ns
t_SWH
t_SWL
t_CLKDV
t_SDH
t_ACQ
t_CSW
t_CDV
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Falling Edge to SDATA Valid
SCLK Falling Edge to SDATA Hold
Acquisition Time (Note 8)
CS Pulse Width
CS Falling Edge to SDATA Valid
0.4 x t_SCLK
0.4 x t_SCLK
10
10
0.6 x t_SCLK ns
0.6 x t_SCLK ns
40
ns
ns
ns
ns
20
ns
Electrical Specifications Limits established by characterization and are not production tested. V_DD = +3.0V to +3.3V, F_SCLK = 15MHz,
F_S = 833kSPS, V_REF = 1.25V, F_IN = 200kHz; V_REF = 2.5V; V_CM = V_REF, T_A = T_MIN to T_MAX unless otherwise noted. Typical values are at T_A = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
fSCLK
t_SCLK
t_CONVERT
Clock Frequency
Clock Period
Conversion Time
16 x t_SCLK
0.05
55
15
MHz
ns
1.07
µs
7
FN8341.0
August 10, 2012