ISL267450_14 Datasheet, PDF (11/19 Pages) Intersil Corporation – 12-Bit, 1MSPS SAR ADCs

ISL267450
Typical Performance Characteristics (Continued)
70000
70000
60000
60000
50000
50000
40000
40000
30000
30000
20000
20000
10000
10000
0
2044
2045
2046 2047 2048
OUTPUT CODE
2049
2050
FIGURE 15. HISTOGRAM OF THE OUTPUT CODES WITH A DC INPUT
FOR V_DD = 5V
0
2044
2045
2046 2047 2048
OUTPUT CODE
2049
2050
FIGURE 16. HISTOGRAM OF THE OUTPUT CODES WITH A DC INPUT
FOR V_DD = 3V
12.0
11.5
11.0
10.5
5V VDD
10.0
3.3V VDD
9.5
9.0
8.5
8.0
7.5
7.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
V_REF (V)
FIGURE 17. CHANGE IN ENOB vs V_REF FOR V_DD = 5V AND 3.3V
Functional Description
The ISL267450 is based on a successive approximation register
(SAR) architecture utilizing capacitive charge redistribution
digital-to-analog converters (DACs). Figure 19 shows a simplified
representation of the converter. During the acquisition phase
(ACQ), the differential input is stored on the sampling capacitors
(CS). The comparator is in a balanced state since the switch
across its inputs is closed. The signal is fully acquired after t_ACQ
has elapsed, and the switches then transition to the conversion
phase (CONV) so the stored voltage may be converted to digital
format. The comparator will become unbalanced when the
differential switch opens and the input switches transition
(assuming that the stored voltage is not exactly at mid-scale).
The comparator output reflects whether the stored voltage is
above or below mid-scale, which sets the value of the MSB. The
SAR logic then forces the capacitive DACs to adjust up or down by
one quarter of full-scale by switching in binarily weighted
capacitors. Again the comparator output reflects whether the
stored voltage is above or below the new value, setting the value
of the next lowest bit. This process repeats until all 12 bits have
been resolved.
-40
-50
-60
-70
-80
-90
-100
-110
10
100
1k
10k
FREQUENCY (kHz)
FIGURE 18. CMRR vs INPUT FREQUENCY FOR V_DD = 5V AND 3V
CONV C_S
VIN+
ACQ
ACQ CONV
ACQ
VIN-
CONV ^CS
VREF
SAR
LOGIC
FIGURE 19. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
11
FN8341.0
August 10, 2012