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| ISL267450_14 Datasheet, PDF (6/19 Pages) Intersil Corporation – 12-Bit, 1MSPS SAR ADCs | |||
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ISL267450
Electrical Specifications VDD = +3.0V to +3.3V, FSCLK = 15MHz, FS = 833kSPS, VREF = 1.25V, FIN = 200kHz; VDD = +4.75V to
+5.25V, FSCLK = 18MHz, FS = 1MSPS, VREF = 2.5V, FIN = 300kHz; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 6)
TYP
(Note 6)
UNITS
ANALOG INPUT (Note 7)
|AIN| Full-Scale Input Span
VIN+, VINâ Absolute Input Voltage Range
VIN+
VINâ
ILEAK
CVIN
Input Leakage Current
Input Capacitance
2 x VREF
VCM = VREF
Track Mode
Hold Mode
VIN+ - VINâ
V
V
VCM ±
V
VREF/2
VCM ±
V
VREF/2
-1
1
µA
12
pF
6
pF
REFERENCE INPUT
VREF
VREF Input Voltage Range
VDD = 5V (±1% tolerance for specified
2.5
V
performance)
VDD = 3V (±1% tolerance for specified
1.25
V
performance)
ILEAK DC Leakage Current
CVREF VREF Input Capacitance
LOGIC INPUTS
-1
1
μA
19
pF
VIH
Input High Voltage
VIL
Input Low Voltage
ILEAK Input Leakage Current
CIN
Input Capacitance
LOGIC OUTPUTS
2.4
V
0.8
V
-1
1
µA
10
pF
VOH
VOL
ILEAK
COUT
Output High Voltage
Output Low Voltage
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
ISOURCE = 200µA
ISINK = 200µA
VDD - 0.3
V
0.4
V
-1
1
µA
10
pF
Twoâs Complement
CONVERSION RATE
tCONV Conversion Time
tACQ
Fmax
Acquisition Time (Note 8)
Throughput Rate
POWER REQUIREMENTS
888ns with FSCLK = 18MHz
1.07µs with FSCLK = 15MHz
Sine Wave Input
VDD = 5V
VDD = 3V
16
SCLK Cycles
16
SCLK Cycles
200
ns
1
MSPS
833
kSPS
VDD
Positive Supply Voltage Range
3.3V ± 10%
5V ± 5%
3.0
3.6
V
4.75
5.25
V
6
FN8341.0
August 10, 2012
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