ISL267450_14 Datasheet, PDF (12/19 Pages) Intersil Corporation – 12-Bit, 1MSPS SAR ADCs

ISL267450
An external clock must be applied to the SCLK pin to generate a
conversion result. The allowable frequency range for SCLK is
50kHz to 18MHz. Serial output data is transmitted on the falling
edge of SCLK. The receiving device (FPGA, DSP or
Microcontroller) may latch the data on the rising edge of SCLK to
maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the V_REF
pin to set the full-scale input range and common-mode voltage.
See “Voltage Reference Input” on page 13 for more details.
ADC Transfer Function
The output coding for the ISL267450 is two’s complement. The
first code transition occurs at successive LSB values (i.e., 1 LSB,
2 LSB, and so on). The LSB size of the ISL267450 is
2*V_REF/4096. The ideal transfer characteristic of the ISL267450
is shown in Figure 20.
V
5.0
4.0
3.0
2.0V_P-P
2.0
1.0
V_IN+
V_REF = 2V
V_IN-
VCM
t
011...111
011...110
1LSB = 2•VREF/4096
000...001
000...000
111...111
100...010
100...001
100...000
–VREF
+ ½LSB
0V
+VREF
– 1½LSB
ANALOG INPUT
VIN+ – (VIN–)
+VREF
– 1LSB
FIGURE 20. IDEAL TRANSFER CHARACTERISTICS
Analog Input
The ISL267450 features a fully differential input with a nominal
full-scale range equal to twice the applied V_REF voltage. Each
input swings V_REF V_P-P, 180° out-of-phase from one another for
a total differential input of 2*V_REF (see Figure 21).
V_CM
V_REF(P-P)
V_REF(P-P)
V_IN+
ISL267450
V_IN-
FIGURE 21. DIFFERENTIAL INPUT SIGNALING
Differential signaling offers several benefits over a single-ended
input, such as:
• Doubling of the full-scale input range (and therefore the
dynamic range)
• Improved even order harmonic distortion
• Better noise immunity due to common mode rejection
V
5.0
4.0
2.5V_P-P
V_IN+
3.0
V_IN-
VCM
2.0
1.0
t
V_REF = 2.5V
FIGURE 22. RELATIONSHIP BETWEEN V_REF AND FULL-SCALE RANGE
Figure 22 shows the relationship between the reference voltage
and the full-scale input range for two different values of V_REF.
Note that there is a trade-off between V_REF and the allowable
common mode input voltage (VCM). The full-scale input range is
proportional to V_REF; therefore the VCM range must be limited for
larger values of V_REF in order to keep the absolute maximum and
minimum voltages on the V_IN+ and V_IN– pins within specification.
Figures 23 and 24 illustrate this relationship for 5V and 3V
operation, respectively. The dashed lines show the theoretical
VCM range based solely on keeping the V_IN+ and V_IN– pins within
the supply rails. Additional restrictions are imposed due to the
required headroom of the input circuitry, resulting in practical
limits shown by the shaded area.
12
FN8341.0
August 10, 2012