ISL267450_14 Datasheet, PDF (15/19 Pages) Intersil Corporation – 12-Bit, 1MSPS SAR ADCs

ISL267450
Serial Interface
Conversion data is accessed with an SPI-compatible serial
interface. The interface consists of the serial clock (SCLK), serial
data output (SDATA), and chip select (CS).
A falling edge on the CS signal initiates a conversion by placing
the part into the acquisition (ACQ) phase. After t_ACQ has elapsed,
the part enters the conversion (CONV) phase and begins
outputting the conversion result starting with a null bit followed
by the most significant bit (MSB) and ending with the least
significant bit (LSB). The CS pin can be pulled high at this point to
put the device into Standby mode and reduce the power
consumption. If CS is held low after the LSB bit has been output,
the conversion result will be repeated in reverse order until the
MSB is transmitted, after which the serial output enters a high
impedance state. The ISL267450 will remain in this state,
dissipating typical dynamic power levels, until CS transitions high
then low to initiate the next conversion.
Data Format
Output data is encoded in two’s complement format as shown in
Table 1. The voltage levels in the table are idealized and don’t
account for any gain/offset errors or noise.
TABLE 1. TWO’S COMPLEMENT DATA FORMATTING
INPUT
VOLTAGE
DIGITAL OUTPUT
–Full Scale
–Full Scale + 1LSB
Midscale
–V_REF
–V_REF + 1LSB
0
1000 0000 0000
1000 0000 0001
0000 0000 0000
+Full Scale – 1LSB
+Full Scale
+V_REF – 1LSB
+V_REF
0111 1111 1110
0111 1111 1111
Application Hints
Grounding and Layout
The printed circuit board that houses the ISL267450 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes since it gives
the best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the
ISL267450 as possible. Avoid running digital lines under the
device, as this will couple noise onto the die. The analog ground
plane should be allowed to run under the ISL267450 to avoid
noise coupling.
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feed-through through the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device.
Terminology
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f_s/2), excluding DC. The ratio is
dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Equation 1:
Signal-to-(Noise + Distortion) = (6.02 N + 1.76)dB
(EQ. 1)
Thus, for a 12-bit converter this is 74dB, and for a 10-bit it is
62dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the ISL267450, it is defined
as Equation 2:
THD(dB) = 20log ^V-----²--²----+-----^V----³---²----+-----^V----⁴--²-----+-----^V----⁵--²----+-----^V-----⁶--²-
V₁₂
(EQ. 2)
where V₁ is the rms amplitude of the fundamental and V₂, V₃,
V₄, V₅, and V₆ are the rms amplitudes of the second to the sixth
harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the rms value of the
fundamental. It is also referred to as Spurious Free Dynamic
Range (SFDR). Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will be
a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m and n = 0, 1, 2 or 3. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).
15
FN8341.0
August 10, 2012