X5323S8IZT1 Datasheet, PDF (7/20 Pages) Intersil Corporation – CPU Supervisor with 32kBit SPI EEPROM

X5323, X5325
SPI Serial Memory
Status Register
The memory portion of the device is a CMOS serial EEPROM
array with Intersil’s block lock protection. The array is
internally organized as x8. The device features a Serial
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus.
The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows:
7
6
5
4
3
2
1
0
The device utilizes Intersil’s proprietary Direct Write^™ cell,
WPEN FLB WD1 WD0 BL1 BL0 WEL WIP
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The Write-In-Progress (WIP) bit is a volatile, read only bit
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
LOW during the entire operation.
The Write Enable Latch (WEL) bit indicates the status of
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the write enable latch. When WEL = 1, the latch is set
HIGH and when WEL = 0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
the user to stop the clock and then start it again to resume
The block lock bits, BL0 and BL1, set the level of block lock
operations where left off.
protection. These nonvolatile bits are programmed using the
Write Enable Latch
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of the
array that is block lock protected can be read but not written. It
will remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
upon a power-up condition and after the completion of a
valid write cycle.
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME INSTRUCTION FORMAT*
OPERATION
WREN
0000 0110
Set the write enable latch (enable write operations)
SFLB
0000 0000
Set flag bit
WRDI/RFLB
0000 0100
Reset the write enable latch/reset flag bit
RSDR
0000 0101
Read status register
WRSR
0000 0001
Write status register (watchdog, block lock, WPEN and flag bits)
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
WREN CMD
WEL
0
1
1
1
STATUS REGISTER
WPEN
X
1
0
X
TABLE 2. BLOCK PROTECT MATRIX
DEVICE PIN
BLOCK
BLOCK
WP
Protected Block Unprotected Block
X
Protected
Protected
0
Protected
Writable
X
Protected
Writable
1
Protected
Writable
STATUS REGISTER
WPEN, BL0, BL1 WD0, WD1
Protected
Protected
Writable
Writable
7
FN8131.2
June 30, 2008