X5323S8IZT1 Datasheet, PDF (13/20 Pages) Intersil Corporation – CPU Supervisor with 32kBit SPI EEPROM

X5323, X5325
Serial Output Timing
2.7 TO 5.5V
PARAMETER
SYMBOL
MIN
MAX
UNIT
Clock Frequency
f_SCK
0
2
MHz
Output Disable Time
t_DIS
250
ns
Output Valid From Clock Low
t_V
250
ns
Output Hold Time
t_HO
0
ns
Output Rise Time
t_RO (Note 3)
100
ns
Output Fall Time
t_FO (Note 3)
100
ns
NOTES:
3. This parameter is periodically sampled and not 100% tested.
4. t_WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
Serial Output Timing
CS
SCK
SO
t_CYC
t_WH
t_LAG
t_V
MSB OUT
t_HO
MSB–1 OUT
t_WL
t_DIS
LSB OUT
SI
ADDR
LSB IN
Power-Up and Power-Down Timing
V_CC
V_TRIP
0V
t_R
RESET (X5323)
t_PURST
t_PURST
RESET (X5323)
V_TRIP
t_F
t_RPD
13
FN8131.2
June 30, 2008