X5323S8IZT1 Datasheet, PDF (14/20 Pages) Intersil Corporation – CPU Supervisor with 32kBit SPI EEPROM

X5323, X5325
RESET Output Timing
SYMBOL
V_TRIP
PARAMETER
Reset Trip Point Voltage, X5323-4.5A, X5323-4.5A
Reset Trip Point Voltage, X5323, X5325
Reset Trip Point Voltage, X5323-2.7A, X5325-2.7A
Reset Trip Point Voltage, X5323-2.7, X5325-2.7
V_TH
V_TRIP Hysteresis (HIGH to LOW vs LOW to HIGH V_TRIP Voltage)
t_PURST Power-up Reset Time-Out
t_RPD (Note 5) V_CC Detect To Reset/Output
t_F (Note 5) V_CC Fall Time
t_R (Note 5) V_CC Rise Time
V_RVALID Reset Valid V_CC
NOTE:
5. This parameter is periodically sampled and not 100% tested.
CS/WDI vs RESET/RESET Timing
CS/WDI
RESET
t_CST
t_WDO
t_RST
t_WDO
MIN
TYP
MAX UNIT
4.5
4.63
4.75
V
4.25
4.38
4.5
V
2.85
2.92
3.0
V
2.55
2.63
2.7
V
20
mV
100
200
280
ms
500
ns
100
µs
100
µs
1
V
t_RST
RESET
RESET/RESET Output Timing
SYMBOL
PARAMETER
t_WDO
Watchdog Time-Out Period
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
t_CST CS Pulse Width to Reset the Watchdog
t_RST Reset Time-Out
MIN
TYP
MAX
UNIT
100
200
300
ms
450
600
800
ms
1
1.4
2
s
400
ns
100
200
300
ms
14
FN8131.2
June 30, 2008