X5323S8IZT1 Datasheet, PDF (10/20 Pages) Intersil Corporation – CPU Supervisor with 32kBit SPI EEPROM

X5323, X5325
CS
SCK
01234567
SI
SO ^{HIGH IMPEDANCE}
FIGURE 7. WRITE ENABLE LATCH SEQUENCE
Symbol Table
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
INSTRUCTION
16-BIT ADDRESS
DATA BYTE 1
15 14 13
3 2 10 7 65 43 2 10
CS
SCK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
SI
7 65 4 32 1 07 6 54 3 21 0
DATA BYTE N
654 321 0
FIGURE 8. WRITE SEQUENCE
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION
DATA BYTE
SI
7 6 5 43 2 1 0
SO
HIGH IMPEDANCE
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
10
FN8131.2
June 30, 2008