X5323S8IZT1 Datasheet, PDF (1/20 Pages) Intersil Corporation – CPU Supervisor with 32kBit SPI EEPROM

®
Data Sheet
X5323, X5325
(Replaces X25323, X25325)
June 30, 2008
FN8131.2
CPU Supervisor with 32kBit SPI EEPROM
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low V_CC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when V_CC falls below the minimum V_CC trip point.
RESET/RESET is asserted until V_CC returns to proper
operating level and stabilizes. Five industry standard V_TRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
Block Diagram
Features
• Selectable watchdog timer
• Low V_CC detection and reset assertion
- Five standard reset threshold voltages
- Re-program low V_CC reset threshold voltage using
special programming sequence
- Reset signal valid to V_CC = 1V
• Determine watchdog or low voltage reset with a volatile
flag bit
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 32kbits of EEPROM
• Built-in inadvertent write protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock^™ protection
- In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 and 1,1)
• Minimize EEPROM programming time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free (RoHS compliant)
WP
SI
SO
SCK
CS/WDI
V_CC
WATCHDOG TRANSITION
DETECTOR
PROTECT LOGIC
DATA
REGISTER
COMMAND
DECODE AND
CONTROL
LOGIC
V_CC THRESHOLD
RESET LOGIC
STATUS
REGISTER
8kBITS
8kBITS
16kBITS
+
V_TRIP
-
WATCHDOG
TIMER RESET
RESET AND
WATCHDOG
TIMEBASE
POWER-ON AND
LOW VOLTAGE
RESET
GENERATION
RESET/RESET
X5323 = RESET
X5325 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.