ISL33001_14 Datasheet, PDF (6/18 Pages) Intersil Corporation – I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability

ISL33001, ISL33002, ISL33003
Test Circuits and Waveforms
- SDA_OUT and SCL pins connected to V_CC
- Enable Delay Time Measured on ISL33001 only
- ISL33003 performance inferred from ISL33001
- If t_DELAY1 < t_EN-LH then t_DELAY2 = t_EN-LH + t_IDLE + t_READY-LH
- If t_DELAY1 > t_EN-LH then t_DELAY2 = t_EN-LH + t_READY-LH
V_CC
V_EN
0.5*V_CC
0V
V_CC
0.5*V_CC
V_{SDA_IN}
V_READY
0.5*V_CC
0V
t_DELAY1
t_READY-LH
t_DELAY2
FIGURE 3. ENABLE DELAY TIME
- V_{SDA_IN} = V_{SDA_OUT} = V_{SCL_OUT} = V_EN = V_CC
- EN Logic Input must be high for t > Enable Delay (t_{EN_LH})
prior to SCL_IN transition
- Bus Idle Time Measured on ISL33001 only
- ISL33002 and ISL33003 performance inferred from ISL33001
V_CC
V_{SCL_IN}
0V
V_CC
V_READY
0V
0.5V_CC
0.5V_CC
t_IDLE
FIGURE 4. BUS IDLE TIME
+3.3V
10kΩ
SCL_OUT
10kΩ
SCL_IN
V_IN
0.2V
V_CC1
10kΩ
SDA_OUT
GND
SDA_IN
V_IN
0.2V
10kΩ
0.2V
SCL_IN OR
SDA_IN
SCL_OUT OR
V_O
SDA_OUT
V_OS = V_O - 0.2V
FIGURE 5A. TEST CIRCUIT
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. INPUT TO OUTPUT OFFSET VOLTAGE
+2.7V
900Ω
SCL_OUT
900Ω
SCL_IN
0V
V_CC1
900Ω
SDA_OUT
GND
SDA_IN
0V
900Ω
SCL_OUT
V_OL
V_OL
SDA_OUT
V_CC1
V_CC1
FIGURE 6A. TEST CIRCUIT
FIGURE 6B. MEASUREMENT POINTS
FIGURE 6. OUTPUT LOW VOLTAGE
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6
FN7560.6
July 11, 2014