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| ISL33001_14 Datasheet, PDF (3/18 Pages) Intersil Corporation – I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability | |||
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ISL33001, ISL33002, ISL33003
Pin Configurations (Continued)
ISL33003
(8 LD TDFN)
TOP VIEW
ISL33003
(8 LD MSOP)
TOP VIEW
VCC2 1
SCL_OUT 2
SCL_IN 3
GND 4
PAD
8 VCC1
7 SDA_OUT
6 SDA_IN
5 EN
VCC2 1
SCL_OUT 2
SCL_IN 3
GND 4
8 VCC1
7 SDA_OUT
6 SDA_IN
5 EN
Pin Descriptions
PIN
PIN NAME NUMBER
FUNCTION
NOTES
VCC1
8
VCC1 power supply, +2.3V to +5.5V. Decouple VCC1 to ground with a high frequency
0.01µF to 0.1µF capacitor.
VCC2
GND
1
VCC2 power supply, +2.3V to +5.5V. Decouple VCC2 to ground with a high frequency ISL33002 (8 LD TDFN, 8 LD MSOP)
0.01µF to 0.1µF capacitor. In level shifting applications, SDA_OUT and SCL_OUT logic ISL33003 (8 LD TDFN, 8 LD MSOP)
thresholds are referenced to VCC2 supply levels. Connect pull-up resistors on these
pins to VCC2.
4 Device Ground Pin
EN
1 Buffer Enable Pin. Logic â0â disables the device. Logic â1â enables the device. Logic ISL33001 (8 LD TDFN, 8 LD SOIC, MSOP)
5
threshold referenced to VCC1.
ISL33003 (8 LD TDFN, 8 LD MSOP)
READY
ACC
SDA_IN
5 Buffer active âReadyâ open drain logic output. When buffer is active, READY is high ISL33001 only
impedance. When buffer is inactive, READY is low impedance to ground. Connect to
10kΩ pull-up resistor to VCC1.
5 Rise Time Accelerator Enable Pin. Logic â0â disables the accelerator. Logic â1â
enables the accelerator. Logic threshold referenced to VCC1.
ISL33002 only
6 Data I/O Pins
SDA_OUT
7
SCL_IN
3 Clock I/O Pins
SCL_OUT
2
PAD
Thermal pad should be connected to ground or floated.
Thermal Pad; TDFN only
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3
FN7560.6
July 11, 2014
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