ISL33001_14 Datasheet, PDF (5/18 Pages) Intersil Corporation – I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability

ISL33001, ISL33002, ISL33003
Electrical Specifications V_EN = V_CC1, V_CC1 = +2.3V to +5.5V, V_CC2 = +2.3V to +5.5V, unless otherwise noted (Note 8). Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
TEMP
MIN
MAX
(°C) (Note 9)
TYP
(Note 9) UNITS
Ready Delay, Off-On
t_READY-LH ISL33001 only (Note 10)
+25
-
Ready Output Low Voltage V_{OL_READY} V_CC1 = +2.5V, I_PULLUP = 3mA; ISL33001 only
Full
-
RISE-TIME ACCELERATORS
10
-
ns
-
0.4
V
Transient Accelerator
I_{TRAN_ACC} V_CC1 = 2.7V, V_CC2 = 2.7V ; (ACC = 0.7*V_CC1 for +25
-
5
-
mA
Current
ISL33002 only) (Figure 8)
Accelerator Pin Enable
Threshold
V_{ACC_EN} ISL33002 only
+25
-
0.5*V_CC1 0.7*V_CC1
V
Accelerator Pin Disable
Threshold
V_{ACC_DIS} ISL33002 only
+25 0.3*V_CC1 0.5*V_CC1
-
V
Accelerator Pin Input
Current
I_ACC
ISL33002 only
+25
-1
0.1
1
µA
Accelerator Delay, On-Off
ESD PROTECTION
t_PDOFF ISL33002 only (Note 10)
+25
-
10
-
ns
SDA, SCL I/O Pins
Human Body Model, SDA and SCL pins to ground +25
-
±12
-
kV
only (JESD22-A114)
All Pins
Machine Model (JESD22-A115)
+25
-
±400
-
V
Class 3 HBM ESD (JESD22-A114)
+25
±6
-
kV
INPUT-OUTPUT CONNECTIONS
Input Low Threshold
Input-Output Offset
Voltage
V_IL
V_CC1 = V_CC2, 10kto V_CC1 on SDA and SCL pins +25
-
V_OS
V_CC1 = 3.3V, 10kto V_CC1 on SDA and SCL pins, Full
0
V_INPUT = 0.2V; V_CC2 = 3.3V, ISL33002 and
ISL33003 (Figure 5)
-
0.3*V_CC1
V
50
150
mV
Output Low Voltage
V_OL
V_CC1 = 2.7V, V_INPUT = 0V, I_SINK = 3mA on
Full
-
SDA/SCL pins; V_CC2 = 2.7V, ISL33002 and
ISL33003 (Figure 6)
-
0.4
V
Buffer SDA and SCL Pins
Input Capacitance
C_IN
(Figure 25)
+25
-
10
-
pF
Input Leakage Current
I_LEAK
SDA and SCL pins = V_CC1 = 5.5V;
V_CC2 = 5.5V, ISL33002 and ISL33003
Full
-5
TIMING CHARACTERISTICS
SCL/SDA Propagation
Delay High-to-Low
t_PHL
C_LOAD = 100pF, 2.7kto V_CC1 on SDA and SCL +25
0
pins, V_CC1 = 3.3V; V_CC2 = 3.3V, ISL33002 and
ISL33003 (Figure 7)
0.1
5
µA
27
100
ns
SCL/SDA Propagation
Delay Low-to-High
t_PLH
C_LOAD = 100pF, 2.7kto V_CC1 on SDA and SCL +25
0
pins, V_CC1 = 3.3V; V_CC2 = 3.3V, ISL33002 and
ISL33003 (Figure 7)
2
26
ns
NOTES:
8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Typical value determined by design simulations. Parameter not tested.
11. Buffer is in the connected state.
12. ISL33002 and ISL33003 limits established by characterization. Not production tested.
13. If the V_CC1 and V_CC2 voltages diverge, then the shut down I_CC increases on the higher voltage supply.
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5
FN7560.6
July 11, 2014