X40410 Datasheet, PDF (5/24 Pages) Intersil Corporation – Dual Voltage Monitor with Intergrated CPU Supervisor

X40410, X40411, X40414, X40415
Resetting the V_TRIPx Voltage
To reset a V_TRIPx voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V_TRIP1 and 0Bh for V_TRIP2, followed by 00h for the
Data Byte in order to reset V_TRIPx. The STOP bit fol-
lowing a valid write operation initiates the program-
ming sequence. Pin WDO must then be brought LOW
to complete the operation.
After being reset, the value of V_TRIPx becomes a nomi-
nal value of 1.7V or lesser.
Note: This operation does not corrupt the memory
array.
CONTROL REGISTER
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, BP1, and BP0. The
X40410/11/14/15 will not acknowledge any data bytes
written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 01Fh,
using the special preamble. Only one byte is read by
each register read operation. The master should sup-
ply a stop condition to be consistent with the bus pro-
tocol, but a stop is not required to end this operation.
7
6
5
4
PUP1 WD1 WD0 BP
3
2
1
0
0 RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 4. Sample V_TRIP Reset Circuit
V_TRIP1
Adj.
V2FAIL
RESET
V_TRIP2
Adj.
4.7K
1
8
3 SOIC 7
2 ^X4041x 6
4
5
V_P
Adjust
Run
µC
SCL
SDA
5
FN8116.0
March 28, 2005