X40410 Datasheet, PDF (10/24 Pages) Intersil Corporation – Dual Voltage Monitor with Intergrated CPU Supervisor

X40410, X40411, X40414, X40415
Figure 9. Byte Write Sequence
Signals from
the Master
SDA Bus
S
t
a
r
Slave
Address
t
0
Byte
Address
S
t
Data
o
p
Signals from
the Slave
A
A
A
C
C
C
K
K
K
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
This means that the master can write 16 bytes to the
page starting at any location on that page. If the master
begins writing at location 10, and loads 12 bytes, then
the first 6 bytes are written to locations 10 through 15,
and the last 6 bytes are written to locations 0 through 5.
Afterwards, the address counter would point to location
6 of the page that was just written. If the master sup-
plies more than 16 bytes of data, then new data over-
writes the previous data, one byte at a time.
Figure 10. Page Write Operation
Signals from
the Master
SDA Bus
S
t
a
r
Slave
Address
t
1 01000 0
Byte
Address
(1 ≤ n ≤ 16)
Data
(1)
S
Data
t
(n)
o
p
Signals from
the Slave
A
A
A
A
C
C
C
C
K
K
K
K
Figure 11. Writing 12 bytes to a 16-byte page starting at location 10.
7 Bytes
address
=6
address pointer
ends here
Addr = 7
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
5 Bytes
address
10
address
n-1
all inputs are disabled until completion of the internal
write cycle. See Figure 10 for the address, acknowl-
edge, and data transfer sequence.
10
FN8116.0
March 28, 2005