X40410 Datasheet, PDF (17/24 Pages) Intersil Corporation – Dual Voltage Monitor with Intergrated CPU Supervisor

X40410, X40411, X40414, X40415
A.C. CHARACTERISTICS
Symbol
Parameter
f_SCL
t_IN
t_AA
t_BUF
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_DH
t_R
t_F
Cb
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive load for each bus line
Note: (1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
t_F
t_HIGH
t_LOW
SCL
t_SU:STA
SDA IN
t_HD:STA
t_SU:DAT
t_HD:DAT
SDA OUT
400kHz
Min.
Max.
0
400
50
0.1
0.9
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb⁽¹⁾
300
20 +.1Cb⁽¹⁾
300
400
t_R
t_AA t_DH
t_SU:STO
t_BUF
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
pF
17
FN8116.0
March 28, 2005