X40410 Datasheet, PDF (12/24 Pages) Intersil Corporation – Dual Voltage Monitor with Intergrated CPU Supervisor

X40410, X40411, X40414, X40415
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 15. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected.
This operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
over” to address 0000_H and the device continues to out-
put data for each acknowledge received. See Figure 15
for the acknowledge and data transfer sequence.
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF_hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF_hex
General Purpose Memory Organization, A8:A0
Address: 00h to 1FFh
General Purpose Memory Array Configuration
Memory Address
A8:A0
000h
0FFh
100h
1FFh
Lower 256 bytes
Upper 256 bytes
Block Protect Option
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 13. X40410/11 Addressing
Slave Byte
General Purpose Memory _{1 0 1 0 0 0 A8 R/W}
Control Register
1 0 1 1 0 0 1 R/W
Fault Detection Register 1 0 1 1 0 0 0 R/W
Word Address
General Purpose Memory _{A7 A6 A5 A4 A3 A2 A1 A0}
Control Register
111 11111
Fault Detection Register 1 1 1 1 1 1 1 1
Figure 14. Current Address Read Sequence
S
Signals from
the Master
t
a
r
Slave
Address
S
t
o
t
p
SDA Bus
10 1000 1
Signals from
the Slave
Data
12
FN8116.0
March 28, 2005