X40410 Datasheet, PDF (2/24 Pages) Intersil Corporation – Dual Voltage Monitor with Intergrated CPU Supervisor

X40410, X40411, X40414, X40415
Low V_CC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
V_CC falls below the minimum V_TRIP1 point. RESET/RE-
SET is active until V_CC returns to proper operating level
and stabilizes. A second voltage monitor circuit tracks
the unregulated supply to provide a power fail warning
or monitors different power supply voltage. Three com-
mon low voltage combinations are available, however,
Intersil’s unique circuits allows the threshold for either
voltage monitor to be reprogrammed to meet special
needs or to fine-tune the threshold for applications re-
quiring higher precision.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features a 2-wire interface and software protocol
allowing operation on an I²C^® bus.
The device utilizes Intersil’s proprietary Direct Write^™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
Triple Voltage Monitors
Device
X4040/11
-A
-B
-C
X40414/15
-A
-B
-C
Expected System Voltages
5V; 3V or 3.3V
5V; 3V
3V; 3.3V; 1.8V
3V; 3.3V; 1.5V
3V; 1.5V
3V or 3.3V; 1.1 or 1.2V
Vtrip1(V)
2.0–4.75*
4.55–4.65*
4.35–4.45*
2.85–2.95*
2.0–4.75*
2.85–2.95*
2.55–2.65*
2.85–2.95*
*Voltage monitor requires V_CC to operation. Others are independent of V_CC.
Vtrip2(V)
1.70–4.75
2.85–2.95
2.55–2.65
1.65–1.75
0.90–3.50*
1.25–1.35*
1.25–1.35*
0.95–1.05*
POR (system)
RESET = X40410
RESET = X40411
RESET = X40414
RESET = X40415
PIN CONFIGURATION
X40410/14, X40411/15
8-Pin SOIC
V2FAIL 1
V2MON ₂
8 V_CC
7 WDO
RESET/RESET 3
V_SS 4
6 SCL
5 SDA
X40410/14, X40411/15
8-Pin TSSOP
WDO 1
V_CC 2
V2FAIL 3
V2MON 4
8 ^SCL
7 SDA
6 V_SS
5 RESET/RESET
PIN DESCRIPTION
Pin
SOIC TSSOP Name
Function
1
3 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V_TRIP2 and
goes HIGH when V2MON exceeds V_TRIP2. There is no power-up reset delay circuitry on this pin.
2
4 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the V_TRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V_SS or V_CC when
not used.The V2MON comparator is supplied by V2MON (X40410/11) or by V_CC Input (X40414/15).
3
5 RESET/ RESET Output. (X40411/15) This is an active LOW, open drain output which goes active whenever
RESET ^VCC ^{falls below V}TRIP1^{. It will remain active until V}CC ^{rises above V}TRIP1 ^{and for the t}PURST ^thereafter.
RESET Output. (X40410/14) This is an active HIGH CMOS output which goes active whenever V_CC
falls below V_TRIP1. It will remain active until V_CC rises above V_TRIP1 and for the t_PURST thereafter.
4
6
V_SS Ground
5
7
SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to
LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transi-
tion within the watchdog time out period results in WDO going active.
2
FN8116.0
March 28, 2005