ISL68201 Datasheet, PDF (5/32 Pages) Intersil Corporation – Single-Phase R4 Digital Hybrid PWM Controller

ISL68201
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL68201IRZ
ISL 68201I
-40 to +85
24 Ld 4x4 QFN
L24.4x4C
ISL68201-99140DEMO1Z
35A Demo Board with On-Board Transient
NOTES:
1. Add “-T” suffix for 6k unit, “-T7A” suffix for 250 unit or “-TK” for 1k unit for Tape and Reel options. Please refer to TB347 for details on reel
specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL68201. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL68201
(24 LD 4X4 QFN)
TOP VIEW
24 23 22 21 20 19
EN 1
18 PROG1
VIN 2
17 PROG2
7VLDO 3
VCC ₄
GND
(PAD)
16 ^PROG3
15 PROG4
SCL 5
14 IOUT
SALERT 6
13 NTC
7 8 9 10 11 12
Functional Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
SYMBOL
DESCRIPTION
EN Precision enable input. Pulling EN above the rising threshold voltage initiates the soft-start sequence, while pulling EN below the
failing threshold voltage suspends the Voltage Regulator (VR) operation.
VIN Input voltage pin for R4 loop and LDOs (5V and 7V). Place a high quality low ESR ceramic capacitor (1.0μF, X7R) in close
proximity to the pin. External series resistor is not advised.
7VLDO 7V LDO from VIN is used to bias current sensing amplifier. Place a high quality low ESR ceramic capacitor (1.0μF, X7R, 10V+)
in close proximity to the pin.
VCC Logic bias supply that should be connected to PVCC rail externally. Place a high quality low ESR ceramic capacitor (1μF,
X7R) from this pin to GND.
SCL Synchronous clock signal input of SMBus/PMBus/I²C.
SALERT Output pin for transferring the active low signal driven asynchronously from the VR controller to SMBus/PMBus.
SDA I/O pin for transferring data signals between SMBus/PMBus/I²C host and VR controller.
PGOOD Power-good open-drain indicator output.
RGND This pin monitors the negative rail of regulator output. Connect to ground at point of regulation.
VSEN This pin monitors the positive rail of regulator output. Connect to point of regulation.
CSRTN This pin monitors the negative flow of output current for overcurrent protection and telemetry.
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5
FN8696.1
March 7, 2016