ISL68201 Datasheet, PDF (10/32 Pages) Intersil Corporation – Single-Phase R4 Digital Hybrid PWM Controller

ISL68201
Operation
The following sections will provide a detailed description of the
ISL68201 operation.
IC Supplies
The ISL68201 has 4 bias pins: VIN, 7VLDO, PVCC and VCC. The
PVCC and 7VLDO voltage rails are 5V LDO and 7.4V LDO supplied
by VIN, respectively, while the VCC pin needs to connect to PVCC
rail externally to be biased. For 5V input applications, all these
pins should be tied together and biased by a 5V supply. Since the
VIN pin voltage information is used by the R4™ Modulator loop,
the user CANNOT bias VIN with a series resistor. In addition, the
VIN pin CANNOT be biased independently from other rails.
Enable and Disable
The IC is disabled until the 7VLDO, PVCC, VCC, VIN and EN pins
increase above their respective rising threshold voltages and the
typical 5.5ms timeout (worst case = 6.5ms) expires, as shown in
Figures 21 and 22 on page 22. The controller will become
disabled when the 7VLDO, PVCC, VCC, VIN or EN pins drop below
their respective falling POR threshold voltages.
The precision threshold EN pin allows the user to set a precision
input UVLO level with an external resistor divider, as shown in
Figure 4. For 5V input applications or wide range input
applications, the EN pin can directly connect to VCC, as shown in
Figure 5. If an external enable control signal is available and is an
open-drain signal, a pull-up impedance (100k or higher) can be
used.
ISL68201
EXTERNAL CIRCUIT
VIN
In addition, based upon ON_OFF_CONFIG [02h] setting, the IC
can be enabled or disabled by series bus command “OPERATION
[01h]” and/or EN pin. See Table 11 on page 25 for more details.
Resistor Reader (Patented)
The ISL68201 offers four programming pins to customize their
regulator specifications. The details of these pins are summarized
in Table 2, followed by the detailed description of resistor reader
operation.
TABLE 2. DEFINITION OF PROG PINS
PIN BIT
NAME
DESCRIPTION
PROG1 [7:0]
BOOT-UP
VOLTAGE
Set output boot-up voltage, 256 different
options: 0, 0.5V to 5.5V (see Table 7)
PROG2 [7:7] PWM/PFM Enables PFM mode or forced PWM.
[6:5] Temperature Adjust NTC temperature compensation:
Compensation OFF, +5, +15, +30°C.
[4:0]
ADDR
Set serial bus 32 different addresses
(see Table 10).
PROG3 [7:7] USPFM Ultrasonic (25kHz Clamp) PFM Enable
[6:6] Fault Behavior OCP fault behavior:
Latch, Infinite 9ms retry
[5:3]
[2:0]
f_SW
R4 Gain
Set switching frequency (f_SW).
Set error amplifier gain (AV).
PROG4 [7:5] RAMP_RATE Set soft-start and DVID ramp rate.
[4:3]
RR
Select RR impedance for R4 loop.
[2:2] AVMLTI Select AV Gain Multiplier (1x or 2x)
[1:0] Not Used
SOFT-
EN
START
VIN UVLO = 10.2V/9.24V
100k
9.09k
FIGURE 4. INPUT UVP CONFIGURATION
Intersil has developed a high resolution ADC using a patented
technique with simple 1%, 100ppm/K or better temperature
coefficient resistor divider. The same type of resistors are
preferred so that it has similar change over-temperature. In
addition, the divider is compared to the internal divider off V_CC
and GND nodes and therefore must refer to V_CC and GND pins,
not through any RC decoupling network.
ISL68201
V_CC
EXTERNAL CIRCUIT
ISL68201
VCC
EXTERNAL CIRCUIT
SOFT-
EN
START
R_EN OPTIONAL
VIN UVLO = 4.20/3.95V
R_EN is ONLY needed when the user wants to
control the IC with an external enable signal
FIGURE 5. 5V INPUT OR WIDE RANGE INPUT CONFIGURATION
REGISTER
TABLE
ADC
R_UP
R_DW
FIGURE 6. SIMPLIFIED RESISTOR DIVIDER ADC
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FN8696.1
March 7, 2016