ISL68201 Datasheet, PDF (30/32 Pages) Intersil Corporation – Single-Phase R4 Digital Hybrid PWM Controller

ISL68201
TABLE 12. DESIGN AND LAYOUT CHECKLIST (Continued)
PIN
NOISE
NAME SENSITIVITY
DESCRIPTION
NTC
YES Place NTC 10k (Murata, NCP15XH103J03RC,
 = 3380) in close proximity to the output
inductor’s output rail, not close to MOSFET side
(see Figure 19); the return trace should be
20 mils away from other traces. Place 1.54kΩ
pull-up and decoupling capacitor (typically
0.1µF) in close proximity to the controller. The
pull-up resistor should be exactly tied to the
same point as VCC pin, not through an RC filter.
If not used, connect this pin to VCC.
IOUT
YES Scale R such that IOUT pin voltage is 2.5V at
63.875A load. Place R and C in general
proximity to the controller. The time constant
of RC should be sufficient as an averaging
function (>200µs) for the digital IOUT. An
external pull-up resistor to VCC placeholder is
recommended cancel IOUT offset at 0A load.
See “IOUT Calibration” on page 19
PROG1-4
NO
Resistor divider must be referenced to VCC pin
and the system ground (GND); they can be
placed anywhere. DO NOT use decoupling
capacitors on these pins.
GND
YES Directly connect to low noise area of the
system ground. The GND PAD should use at
least 4 vias. Separate analog ground and
power ground with a 0Ω resistor is highly NOT
recommended.
FCCM
NO
DO NOT make it across or under external
components of the controller. Keep it at least
20 mils away from sensitive nodes.
PWM
NO
DO NOT make it across or under external
components of the controller. Keep it at least
20 mils away from any other traces.
LGIN
NO
Keep it at least 20 mils away from sensitive
nodes. A series 100Ω resistor to low-side gate
signal is required for noise attenuation.
PVCC
YES Place X7R 4.7µF in proximity to PVCC pin and
the system ground plane.
TABLE 13. TOP LAYOUT TIPS (Continued)
NUMBER
DESCRIPTION
5 Place all decoupling capacitors in close proximity to the
controller and the system ground plane.
6 Connect remote sense (VSEN and RGND) to the load and
ceramic decoupling capacitors nodes; never run this pair
above or below switching noise plane.
7 Always double check critical component pinout and their
respective footprints.
Voltage Regulator Design Materials
To support VR design and layout, Intersil also developed a set of
tools and evaluation boards, as listed in Tables 14 and 15,
respectively. Contact Intersil’s local office or field support at
www.intersil.com/ask for the latest available information.
TABLE 14. AVAILABLE DESIGN ASSISTANCE MATERIALS
ITEM
1
DESCRIPTION
SMBus/PMBus/I²C communication tool with
PowerNavigator™ GUI
2
Evaluation board schematics in OrCAD format and
layout in allegro format. See Table 15 for details.
TABLE 15. AVAILABLE DEMO BOARDS
DEMO BOARD
ISL68200DEMO1Z
ISL68201-99140DEMO1Z
DESCRIPTION
17x17mm² 1-phase, 20A solution;
400kHz, with Dual FET
17x17mm² 1-phase, 35A solution;
400kHz, with ISL99140
TABLE 13. TOP LAYOUT TIPS
NUMBER
DESCRIPTION
1 The layer next to controller (top or bottom) should be a ground
layer. Separate analog ground and power ground with a 0Ω
resistor is highly NOT recommended. Directly connect GND
PAD to low noise area of the system ground with at least 4
vias.
2 Never place controller and its external components above or
under VIN plane or any switching nodes.
3 Never share CSRTN and VSEN on the same trace.
4 Place the input rail decoupling ceramic capacitors closely to
the high-side FET on the same layer as possible. Never use
only one via and a trace connect the input rail decoupling
ceramics capacitors; must connect to VIN and GND planes.
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FN8696.1
March 7, 2016