ISL68201 Datasheet, PDF (28/32 Pages) Intersil Corporation – Single-Phase R4 Digital Hybrid PWM Controller

ISL68201
General Application Design
Guide
This design guide is intended to provide a high-level explanation of
the steps necessary to design a single-phase buck converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced in the following. In addition to this
guide, Intersil provides complete reference designs that include
schematics, bills of materials and example board layouts.
Output Filter Design
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because it
has a low bandwidth compared to the switching frequency, the
output filter necessarily limits the system transient response. The
output capacitor must supply or sink load current while the
current in the output inductors increases or decreases to meet
the demand.
In high-speed converters, the output capacitor bank is usually the
most costly (and often the largest) part of the circuit. Output filter
design begins with minimizing the cost of this part of the circuit.
The critical load parameters in choosing the output capacitors are
the maximum size of the load step, I; the load current slew rate,
di/dt; and the maximum allowable output voltage deviation under
transient loading, V_MAX. Capacitors are characterized according
to their capacitance, ESR and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. The capacitors selected must have sufficiently low ESL and
ESR so that the total output voltage deviation is less than the
allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount, as shown in Equation 15:
V  I  ESR + -_L-^E---_O--^S--_U--^L--_T--  V_IN + -_C-----_O-¹---_U----_T--  -₈----_-----_N---^--_--^I---_f--_S---_W----
(EQ. 15)
I= -^V----^O_L----_OU----_UT----_T-^----_---¹-_f--_S--–--_W--^D-----^
The filter capacitor must have sufficiently low ESL and ESR so
that V < V_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination with bulk
capacitors having high capacitance but limited high-frequency
performance. Minimizing the ESL of the high-frequency capacitors
allows them to support the output voltage as the current increases.
Minimizing the ESR of the bulk capacitors allows them to supply the
increased current with less output voltage deviation. The ESR of the
bulk capacitors also creates the majority of the output voltage
ripple. As the bulk capacitors sink and source the inductor AC
ripple current, a voltage develops across the bulk capacitor ESR
equal to I_C(P-P) (ESR).
Thus, once the output capacitors are selected, the maximum
allowable ripple voltage, V_P-P(MAX), determines the lower limit on
the inductance, as shown in Equation 16.
L_OUT  ESR  _f--VS----_WO-----^U--_--^T--V---^-_I--_N-^---V-_---^I--V^N----_P--^–--_–---_P^V---_-^O-_M---^U--_A---^T-_X--^--_
(EQ. 16)
Since the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
before the output voltage decreases more than V_MAX. This
places an upper limit on inductance.
Equation 17 gives the upper limit on L for cases when the trailing
edge of the current transient causes a greater output to voltage
deviation than the leading edge. Equation 18 addresses the
leading edge. Normally, the trailing edge dictates the selection of
L because duty cycles are usually less than 50%. Nevertheless,
both inequalities should be evaluated, and L should be selected
based on the lower of the two results. In each equation, L is the
per-channel inductance, C is the total output capacitance..
L_OUT  ^2----------C-_---_-^---I--V_--₂--^O----^U-----^T- V_MAX – I  ESR
(EQ. 17)
L_OUT  ^1----._--2-_--5--I--_-^-₂---C---
V_MAX – I  ESR


V_I
N
–
V_O
U
T_
(EQ. 18)
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper MOSFETs.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the upper MOSFETs, which is
related to duty cycle and the number of active phases. The input
RMS current can be calculated with Equation 19.
I_{IN RMS} = D – D²ï€©  Io² + ₁--^D--₂--  I²
(EQ. 19)
Use Figure 30 to determine the input capacitor RMS current
requirement given the duty cycle, maximum sustained output
current (I_O), and the ratio of the per-phase peak-to-peak inductor
current (I_L(P-P) to I_O. Select a bulk capacitor with a ripple current
rating, which will minimize the total number of input capacitors
required to support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25x greater than the
maximum input voltage.
Low capacitance, high-frequency ceramic capacitors are needed
in addition to the bulk capacitors to suppress leading and falling
edge voltage spikes. The result from the high current slew rates
produced by the upper MOSFETs turn on and off. Select low ESL
ceramic capacitors and place one as close as possible to each
upper MOSFET drain to minimize board parasitic impedances
and maximize noise suppression.
Submit Document Feedback ₂₈
FN8696.1
March 7, 2016