ISL68201 Datasheet, PDF (20/32 Pages) Intersil Corporation – Single-Phase R4 Digital Hybrid PWM Controller

ISL68201
by the equivalent impedance of R_{IOUT_UP}//R_{IOUT_DW} = R_IOUT
(as in Figure 20); the slope of the ideal curve should set to 1A/A
with 0A offset.
For a precision digital I_OUT, follow the fine-tuned procedure below
step-by-step; steps 1 to 5 must be completed before step 6.
1. Properly tune L/DCR or ESL/R_SEN matching as shown on
page 17 over the range of temperature operation. +25% over-
matching L/DCR at room temperature is needed for -40°C
operation.
2. Properly complete thermal compensation as shown on
“Thermal Monitoring and Compensation” on page 17.
3. Finalize R_ISEN resistor to set OCP for overall operating
conditions and board variations as shown on “Overcurrent
and Short-Circuit Protection” on page 20.
4. Collect no load I_OUT current with sufficient prototypes and
determine the mean of no load I_OUT current.
5. The pull-up impedance on IOUT pin should be
“VCC/IOUT_NO_LOAD”; for instance, a mean of -2.5µA I_OUT at
0A load, it will need R_{IOUT_UP} = 2MΩ.
6. Start with the value below and then fine tune the R_{IOUT_DW}
value until the average slope of various boards equals 1A/A.
R_{IOUT_DW} = ^R-_R----^II--^OO----^U-_U----^TT---^__---^UU----^PP----^x_–---RR-----_II--_OO----_UU----_TT--
(EQ. 13)
Fault Protection
The ISL68201 provides high system reliability with many fault
protections, as summarized in Table 9.
TABLE 9. FAULT PROTECTION SUMMARY
FAULT
DESCRIPTION
FAULT ACTION
Input UVLO
VIN pin UVLO; or set by EN pin Shutdown and recover
with an external divider for higher when VIN > UVLO
level. See Figures 4 and 5.
Bias UVLO VCC, PVCC, 7VLDO UVLO
Shutdown and recover
when Bias > UVLO
Start-Up OVP Higher than V_BOOT. See Electrical Latch OFF, reset by VCC
Specifications on page 7.
or toggling enable
(including EN pin and/
Output OVP Rising = 120%; Falling = 100% _{or OPERATION}
Output UVP 74% of V_OUT, Latch OFF
command based upon
ON_OFF_CONFIG
setting)
Output OCP Average OCP = 100µA with
128µs blanking time.
Short-Circuit Peak OCP = 130% of Average
Protection OCP with 50ns filter.
Latch OFF (reset by VCC
or toggling enable
including EN pin and/
or OPERATION
command based upon
ON_OFF_CONFIG
setting), or retry every
9ms; option is
programmable by
PROG3 or D3[0]
OTP
Rising = 22.31%VCC (~+136°C); Shut down above
Falling =27.79%VCC (~+122°C). +136°C and recover
when temperature
drops below +122°C
UVLO and OTP faults will respond to the current state with
hysteresis, while output OVP and output UVP faults are latch
events, while output OCP and output short-circuit faults can be
latch or retry events depending upon PROG3 or D3[0] setting. All
fault latch event can be reset by VCC cycling, toggling Enable pin
and/or series bus OPERATION command based upon
ON_OFF_CONFIG setting, while the OCP retry event has a hiccup
time of 9ms and the regulator can be recovered when the fault is
removed.
OVERVOLTAGE PROTECTION
The OVP fault detection circuit triggers after the voltage between
VSEN+ and VSEN- is above the rising overvoltage threshold.
When an OVP fault is declared, the controller will be latched off
and the PGOOD pin will be asserted low. The fault will remain
latched and can be reset by VCC cycling or toggling EN pin and/or
series bus OPERATION command based upon ON_OFF_CONFIG
setting_.
Although the controller has latched off in response to an OVP
fault, the LGATE gate-driver output will retain the ability to toggle
the low-side MOSFET on and off, in response to the output
voltage transversing the OVP rising and falling thresholds. The
LGATE gate driver will turn on the low-side MOSFET to discharge
the output voltage, protecting the load. The LGATE gate driver will
turn off the low-side MOSFET once the sensed output voltage is
lower than the falling overvoltage threshold (typically 100%). If
the output voltage rises again, the LGATE driver will again turn on
the low-side MOSFET when the output voltage is above the rising
overvoltage threshold (typically 120%). By doing so, the IC protects
the load when there is a consistent overvoltage condition.
In addition to normal operation OVP, 5.5ms (typically, worst
6.5ms) after all rails (VCC, PVCC, 7VLDO, VIN) POR and prior to
the end of soft-start, the start-up OVP circuits are enabled to
protect against OVP event, while the OVP level is set higher than
V_BOOT. See Electrical Specifications on page 7.
UNDERVOLTAGE PROTECTION
The UVP fault detection circuit triggers after the output voltage is
below the undervoltage threshold (typically 74% of DAC). When
an UVP fault is declared, the controller will be latched off, forcing
the LGATE and UGATE gate-driver outputs low, and the PGOOD
pin will be asserted low. The fault will remain latched and can be
reset by VCC cycling or toggling EN pin and/or series bus
OPERATION command based upon ON_OFF_CONFIG setting.
OVERCURRENT AND SHORT-CIRCUIT PROTECTION
The average Overcurrent Protection (OCP) is triggered when the
internal current out of the IOUT pin goes above the fault
threshold (typically 100µA) with 128µs blanking time. It also has
a fast (50ns filter) secondary overcurrent protection whose
threshold is +30% above average OCP; this protects inductor
saturation from a short-circuit event and provides a more robust
power train and system protection. When an OCP or short-circuit
fault is declared, the controller will be latched off, forcing the
LGATE and UGATE gate-driver outputs low, or retry with a hiccup
time of 9ms; the fault response is programmable by PROG3 or
D3[0]. The latched off event however can be reset by VCC cycling
or toggling EN pin and/or series bus OPERATION command
based upon ON_OFF_CONFIG setting_.
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FN8696.1
March 7, 2016