HMP8117 Datasheet, PDF (39/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
Pin Descriptions (Continued)
PIN
NAME
LCAP
PIN
NUMBER I/O
76
I
PASSIVE
0.1 F
to AGND
CCAP
29
I
0.1 F
to AGND
P0-P15
42, 43, 45,
47-51, 54-58, O
60, 63, 64
HSYNC
71
O
N/A
10KΩ Pullup
VSYNC
70
O 10KΩ Pullup
FIELD
67
O 10KΩ Pullup
DVALID
66
O 10KΩ Pullup
BLANK
65
O 10KΩ Pullup
VBIVALID
61
O 10KΩ Pullup
INTREQ
CLK2
RESET
SA
SDA
SCL
VAA
44
38
34
27
40
41
2, 12, 14
O 10KΩ Pullup
I
I
10KΩ Pullup
I
or
0Ω Pulldown
I/O 4KΩ Pullup
I
4KΩ Pullup
0.1 F
I
to AGND
DESCRIPTION
Storage capacitor for Luminance signal DC restoration. The LCAP voltage offsets the sync
tip to the lower reference of the A/D. A 0.1µF capacitor should be connected between this
pin and AGND. This capacitor should be as close to this pin as possible for best
performance.
Storage capacitor for Chrominance signal DC restoration. The CCAP voltage offsets the
chroma signal to mid-range of the A/D. A 0.1µF capacitor should be connected between
this pin and AGND. This capacitor should be as close to this pin as possible for best
performance.
Pixel output pins. See Table 3. These pins are three-stated after a RESET or software
reset.
Horizontal sync output. HSYNC is asserted during the horizontal sync intervals. The
polarity of HSYNC is programmable. This pin is three-stated after a RESET or software
reset and should be pulled high through a 10KΩ resistor.
Vertical sync output. VSYNC is asserted during the vertical sync intervals. The polarity of
VSYNC is programmable. This pin is three-stated after a RESET or software reset and
should be pulled high through a 10KΩ resistor.
FIELD output. The polarity of FIELD is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10KΩ resistor.
Data valid output. DVALID is asserted during CLK2 cycles that contain valid pixel data. This
pin is three-stated after a RESET or software reset and should be pulled high through a
10KΩ resistor.
Composite blanking output. BLANK is asserted during the horizontal and vertical blanking
intervals. The polarity of BLANK is programmable. This pin is three-stated after a RESET
or software reset and should be pulled high through a 10KΩ resistor.
Vertical Blanking Interval Valid output. VBIVALID is asserted during CLK2 cycles that
contain valid VBI (Vertical Blanking Interval) data such as Closed Captioning, Teletext, and
WSS data. The polarity of VBIVALID is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10K resistor.
Interrupt Request Output. This is an open-drain output and requires an external 10KΩ pull-
up resistor to V_CC.
2x pixel clock input. This clock must be a continuous, free-running clock. Refer to Table 1
for allowable CLK2 frequencies for each video standard and aspect ratio. For best
performance, use termination resistor(s) to minimize pulse overshoot and reflections.
Reset control input. A logical zero for a minimum of four CLK2 cycles resets the device.
RESET must be a logical one for normal operation.
I²C slave address select input. This was formerly the WPE pin on HMP8112/15 decoders.
If the SA pin is pulled low, the I²C address is 1000100xB or 88_H. If the SA pin is pulled high,
the address is 1000101xB or 8A_H. (The ‘x’ bit is the address is the I2C read flag.)
I²C data input/output. This pin should be pulled high through a 4KΩ resistor.
I²C clock input. This pin should be pulled high through a 4KΩ resistor.
Analog power supply pins. All VAA pins must be connected together.
AGND 1, 3, 10, 11,
15,16, 21, 22, I
23, 24
VCC
26, 31,37, 52,
59, 68, 75, 79
I
GND
25, 33, 35, 36,
39, 46, 53, 62, I
69, 72, 80
NC
4, 13, 18,
20, 30, 32,
73, 74, 77
none
Analog ground pins. All AGND pins must be connected together. Refer to Applications
section for recommended grounding scheme.
Digital power supply pins. All VCC pins must be connected together.
Digital ground pins. All GND pins must be connected together.
No Connect pins. These pins may be left floating or tied to GND.
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