HMP8117 Datasheet, PDF (12/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
Pixel Output Port
Pixel data is output via the P0-P15 pins. Refer to Table 4 for
the output pin definition as a function of the output mode.
Refer to the section “CYCLE SLIPPING AND REAL-TIME
PIXEL JITTER” for PLL and interface considerations.
8-Bit YCbCr Output
Each YCbCr data byte is output following each rising edge of
CLK2. The YCbCr data is multiplexed as [Cb Y Cr Y′ Cb Y Cr
CLK
Y′...], with the first active data each scan line containing Cb
data. The pixel output timing is shown in Figures 8 and 9.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr. The behavior
of the DVALID output is determined by bit 4 (DVLD_LTC) of
the GENLOCK CONTROL register 04_H.
DVALID
BLANK
P[15-8]
Cb₀
Y₀
Cr₀
Y₁
Cb₂
Y₂
Cr₂
Y₃
Cb₄
Y₄
NOTE:
t_DVLD
5. Y₀ is the first active luminance pixel data of a line. Cb₀ and Cr₀ are first active chrominance pixel data in a line. Cb and Cr will alternate every
cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values are forced to blanking levels.
FIGURE 8. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 0)
16-Bit YCbCr, 15-Bit RGB, or 16-RGB Output
For 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB output
modes, the data is output following the rising edge of CLK2
with DVALID asserted. Either linear or gamma-corrected
RGB data may be output. The pixel output timing is shown in
Figures 10 to 13.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
CLK
DVALID
BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr; the RGB
outputs have a value of 0.
The behavior of the DVALID output is determined by bit 4
(DVLD_LTC) and bit 5 (DLVD_DCYC) of the GENLOCK
CONTROL register 04_H.
P[15-8]
Cb₀
Y₀
Cr₀
Y₁
Cb₂
Y₂
Cr₂
Y₃
Cb₄
Y₄
NOTES:
t_DVLD
6. Y₀ is the first active luminance pixel data of a line. Cb₀ and Cr₀ are first active chrominance pixel data in a line. Cb and Cr will alternate every
cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values are forced to blanking levels.
7. When DVLD_LTC is set to 1, the polarity of DVALID needs to be set to active low, otherwise DVALID will stay low during active video and be
gated with the clock only during the blanking interval.
FIGURE 9. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 1)
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