HMP8117 Datasheet, PDF (35/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
BIT
NO.
FUNCTION
7-6
Reserved
5-0
Even Field
WSS CRC Data
BIT
NO.
FUNCTION
7-0
Assert BLANK
Output Signal
BIT
NO.
15-10
9-8
FUNCTION
Reserved
Assert BLANK
Output Signal
BIT
NO.
FUNCTION
7-0
Negate BLANK
Output Signal
BIT
NO.
FUNCTION
7-0
Assert BLANK
Output Signal
BIT
NO.
15-9
8
FUNCTION
Reserved
Assert BLANK
Output Signal
TABLE 52. WSS_CRC_EVEN DATA REGISTER
SUB ADDRESS = 29_H
DESCRIPTION
If even field WSS is enabled and present during NTSC operation, this register is loaded with the
six bits of CRC information on line 283. It is always a “000000” during PAL operation. Data written
to this register is ignored.
RESET
STATE
00_B
000000_B
TABLE 53. START H_BLANK LSB REGISTER
SUB ADDRESS = 30_H
DESCRIPTION
This 8-bit register is cascaded with Start H_BLANK High Register to form a 10-bit start horizontal
blank REGISTER. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK
each scan line. Bit 0 is always a “0”, so the start of horizontal blanking may only be done with two
pixel resolution. The leading edge of HSYNC is count 000_H.
TABLE 54. START H_BLANK MSB REGISTER
SUB ADDRESS = 31_H
DESCRIPTION
This 2-bit register is cascaded with Start H_BLANK Low Register to form a 10-bit start horizontal
blank register. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK each
scan line. The leading edge of HSYNC is count 000_H.
TABLE 55. END H_BLANK REGISTER
SUB ADDRESS = 32_H
DESCRIPTION
This 8-bit register specifies the horizontal count (in 1x clock cycles) to negate BLANK each scan
line. For proper operation, bit 0 must always be set to “0”; therefore, the end of horizontal
blanking may only set with two pixel resolution. If bit 0 is set to “1”, the chroma/luma output data
may be swapped. The leading edge of HSYNC is count 000_H.
TABLE 56. START V_BLANK LSB REGISTER
SUB ADDRESS = 33_H
DESCRIPTION
This 8-bit register is cascaded with Start V_BLANK High Register to form a 9-bit start vertical
blank register. It specifies the line number to assert BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For
PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields.
RESET
STATE
4A_H
RESET
STATE
000000_B
11_B
RESET
STATE
7A_H
RESET
STATE
02_H
TABLE 57. START V_BLANK MSB REGISTER
SUB ADDRESS = 34_H
DESCRIPTION
This 1-bit register is cascaded with Start V_BLANK Low Register to form a 9-bit start vertical
blank register.
RESET
STATE
0000000_B
1_B
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