HMP8117 Datasheet, PDF (25/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
TABLE 15. GENLOCK CONTROL REGISTER
BIT
NO.
FUNCTION
SUB ADDRESS = 04_H
DESCRIPTION
RESET
STATE
7
Aspect Ratio
0 = Rectangular (BT.601) pixels
0_B
Mode
1 = Square pixels
6
Freeze Output
Timing Enable
Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit to a “0”
0_B
resumes normal operation at the start of the next field.
0 = Normal operation
1 = Freeze output timing
5
DVALID Duty Cycle This bit is ignored during the 8-bit YCbCr and BT.656 output modes.
0_B
Control
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
(DVLD_DCYC)
0 = DVALID has 50/50 duty cycle at the pixel output data rate
1 = DVALID goes active based on line-lock. This will cause DVALID to not have a 50/50 duty
cycle. This bit is intended to be used in maintaining backward compatibility with the HMP8112A
DVALID output timing.
4
DVALID Line Timing During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0_B
Control
0 = DVALID present only during active video time on active scan lines
(DVLD_LTC)
1 = DVALID present the entire scan line time on all scan lines
During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output as:
0 = Normal timing
1 = DVALID signal ANDed with CLK2
3
Missing HSYNC
This bit specifies the number of missing horizontal sync pulses before entering horizontal lock
1_B
Detect Select
acquisition mode.
0 = 12 pulses
1 = 1 pulse
2
Missing VSYNC
This bit specifies the number of missing vertical sync pulses before entering vertical lock
0_B
Detect Select
acquisition mode.
0 = 3 pulses
1 = 1 pulse
1-0
CLK2 Frequency This bit indicates the frequency of the CLK2 input clock.
01_B
00 = 24.54MHz10 = 29.5MHz
01 = 27.0MHz11 = Reserved
TABLE 16. ANALOG INPUT CONTROL REGISTER
BIT
NO.
FUNCTION
SUB ADDRESS = 05_H
DESCRIPTION
RESET
STATE
7-6
Lock Loss
Video Gain
Select
If bits 5-4 do not equal “01”, these bits indicate what mode the AGC circuitry will be after loss of
00_B
sync. If bits 5-4 equal “01”, these bits are ignored.
00 = Automatic gain control: bits 5-4 will be reset to “01”
01 = Maintain fixed gain: bits 5-4 will not be changed
10 = Normal AGC switching to fixed gain after lock achieved: bits 5-4 will not be reset to “01”
unless they indicated “freeze automatic gain control”
11 = reserved
5-4
Video Gain
00 = Fixed 1x gain
01_B
Control Select
01 = Automatic gain control
10 = Fixed gain control. (Use gain factor from Video Gain Adjust register 1D_H.)
11 = Freeze automatic gain control
3
Digital Anti-Alias 0 = Internal digital anti-alias filter is active.
0_B
Filter Control
1 = Internal digital anti- alias filter is bypassed. (Not Recommended)
2-0
Video Signal
Input Select
000 = CVBS1
001 = CVBS2
010 = CVBS3
011 = S-video
1XX = reserved
000_B
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