HMP8117 Datasheet, PDF (21/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
SDA must be pulled high using external 4kΩ pull-up
resistors. The SA input pin determines the slave address for
the HMP8117. If the SA pin is pulled low, the address is
1000100x_B. If the SA pin is pulled high through a 10kΩ pull-
up resistor, the address is 1000101x_B. (This ‘x’ bit in the
address is the I²C read flag.)
Data is placed on the SDA line when the SCL line is low and
held stable when the SCL line is pulled high. Changing the
state of the SDA line while SCL is high will be interpreted as
either an I²C bus START or STOP condition as indicated by
Figure 18.
During I²C write cycles, the first data byte after the slave
address is treated as the control register sub address and is
written into the internal address register. Any remaining data
bytes sent during an I²C write cycle are written to the control
t_BUF
t_SU:DATA
SDA
t_HD:DATA
registers, beginning with the register specified by the
address register as given in the first byte. The address
register is then auto-incremented after each additional data
byte sent on the I²C bus during a write cycle. Writes to
reserved bits within registers or reserved registers are
ignored.
In order to perform a read from a specific control register
within the HMP8117, an I²C bus write must first be
performed to properly setup the address register. Then an
I²C bus read can be performed to read from the desired
control register(s). As a result of needing the write cycle for a
read cycle there are actually two START conditions as
shown in Figure 19. The address register is then auto-
incremented after each byte read during the I²C read cycle.
Reserved registers return a value of 00_H.
SCL
t_LOW t_HIGH
t_R t_F
FIGURE 17. I²C TIMING DIAGRAM
tSU:STOP
SDA
SCL
S
1-7
8
9
1-7
8
START
ADDRESS
R/W
CONDITION
ACK
DATA
FIGURE 18. I²C SERIAL DATA FLOW
9
ACK
P
STOP
CONDITION
21