HMP8117 Datasheet, PDF (10/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
NTSC(M) LINE# 262
263
264
265
266
267
268
269
270
271
272
273
PAL(M) LINE# ₂₅₉
260
261
262
263
264
265
266
267
268
269
270
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
FIGURE 4. NTSC(M) AND PAL(M) EVEN FIELD TIMING
LINE #
621
622
623
624
625
1
2
3
4
5
6
7
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘EVEN’ FIELD
‘ODD’ FIELD
FIGURE 5. PAL(B, D, G, H, I, N, N_C) ODD FIELD TIMING
LINE #
309
310
311
312
313
314
315
316
317
318
319
320
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
FIGURE 6. PAL(B, D, G, H, I, N, N_C) EVEN FIELD TIMING
BLANK and DVALID Timing
DVALID is asserted when P15-P0 contain valid data. The
behavior of the DVALID output is determined by bit 4
(DVLD_LTC) and bit 5 (DLVD_DCYC) of the GENLOCK
CONTROL register 04_H for each video output mode.
The BLANK output pin is used to distinguish the blanking
interval period from active video data. The blanking intervals
are programmable in both horizontal and vertical
dimensions. Reference Figure 7 for active video timing and
use Table 3 for typical blanking programming values.
During active scan lines, BLANK is asserted when the
horizontal pixel count matches the value in the START
H_BLANK register 31_H/30_H. The pixel counter is 000_H at the
leading edge of the sync tip after a fixed pipeline delay. Since
blanking normally occurs on the front porch, (prior to count
000H) the START H_BLANK count must be programmed
with a large value from the previous line. Refer to the Last
Pixel Count from Table 3. BLANK is negated when the
horizontal pixel count matches the value in the END
H_BLANK register 32_H. Note that horizontally, BLANK is
programmable with two pixel resolution.
START V_BLANK register 34_H/33_H and END V_BLANK
register 35_H determine which scan lines are blanked for each
field. During inactive scan lines, BLANK is asserted during the
entire scan line. Half-line blanking of the output video cannot
be done.
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