ISL28025 Datasheet, PDF (38/47 Pages) Intersil Corporation – Precision Digital Power Monitor with Real Time Alerts

ISL28025
SIGNALS
FROM THE
MASTER
S
T ^{IDENTIFICATION}
A
BYTE WITH
R
R/W = 0
T
ADDRESS
BYTE
S
T IDENTIFICATION
A
BYTE WITH
R
R/W = 1
T
S
A
T
C
O
K
P
SIGNAL AT
SDA
1nnnnnn0
A
SIGNALS FROM
C
THE SLAVE
K
1nnnnnn1
A
A
C
K
C
K
FIRST READ
DATA BYTE
FIGURE 73. READ SEQUENCE (SLAVE ADDRESS SHOWN AS nnnn)
SECOND READ
DATA BYTE
The last bit of the slave address byte defines a read or write
operation to be performed. When this R/W bit is a “1”, a read
operation is selected. A “0” selects a write operation (refer to
Figure 72).
After loading the entire slave address byte from the SDA bus, the
device compares with the internal slave address. Upon a correct
compare, the device outputs an acknowledge on the SDA line.
Following the slave byte is a one byte word address. The word
address is either supplied by the master device or obtained from an
internal counter. On power-up, the internal address counter is set to
address 00h, so a current address read starts at address 00h. When
required, as part of a random read, the master must supply the one
word address bytes, as shown in Figure 73.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the registers, the slave byte must be “1nnnnnnx” in
both places.
Write Operation
A write operation requires a START condition, followed by a valid
identification byte, a valid Address byte, two data bytes and a
STOP condition. The first data byte contains the MSB of the data,
the second contains the LSB. After each of the four bytes, the
device responds with an ACK. At this time, the I²C interface
enters a standby state.
Read Operation
A read operation consists of a three byte instruction, followed by
two data bytes (see Figure 73). The master initiates the operation
issuing the following sequence: A START, the identification byte
with the R/W bit set to “0”, an address byte, a second START and a
second identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL28025 responds with an ACK. Then the
ISL28025 transmits two data bytes as long as the master
responds with an ACK during the SCL cycle following the eighth bit
of the first byte. The master terminates the read operation (issuing
no ACK then a STOP condition) following the last bit of the second
data byte (see Figure 73).
The data bytes are from the memory location indicated by an
internal pointer. This pointer’s initial value is determined by the
address byte in the read operation instruction and increments by
one during transmission of each pair of data bytes.
SLAVE ADDRESS
1
n
n
n
nn
n
R/W _BYTE
A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS
D15 D14 D13 D12 D11 D10 D9 D8 DATA BYTE 1
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE 2
FIGURE 74. SLAVE ADDRESS, WORD ADDRESS AND DATA BYTES
Group Command
The DPM has a feature that allows the master to configure the
settings of all DPM chips at once. The configuration command for
each device does not have to be same. Device 1 on an I²C bus could
be configured to set the voltage threshold of the OV comparator
while device 2 is configured for the acquisition time of the V_BUS
input. To achieve the scenario described without group command,
the master sends two write commands, one to each slave device.
Each command sent from the master has a start bit and a stop bit.
The group command protocol concatenates the two commands but
replaces the stop bit of the first command and the start bit of the
second command with a repeat start bit. The actions sent in a Group
Command format will execute once the stop bit has been sent. The
stop bit signifies the end of a packet.
The broadcast feature saves time in configuring the DPM as well
as measuring signal parameters in time synchronization. The
broadcast should not be used for DPM read backs. This will
cause all devices connected to the I²C bus to talk to the master
simultaneously.
Clock Speed
The device supports high-speed digital transactions up to
3.4Mbs. To access the high speed I²C feature, a master byte
code of 0000 1xxx is attached to the beginning of a standard
frequency read/write I²C protocol. The x in the master byte
signifies a do not care state. X can either equal a 0 or a 1. The
master byte code should be clocked into the chip at frequencies
equal or less than 400kHz. The master code command
configures the internal filters of the ISL28025 to permit data bit
frequencies greater than 400kHz. Once the master code has
been clocked into the device, the protocol for a standard read/
write transaction is followed. The frequency at which the
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FN8388.3
June 17, 2015