ISL28025 Datasheet, PDF (25/47 Pages) Intersil Corporation – Precision Digital Power Monitor with Real Time Alerts

ISL28025
FIGURE 65. BLOCK READ SMBUS PROTOCOLS WITH AND WITHOUT PEC.
NOTE: Diagrams copied from SMBus specification document. The document can be uploaded at http://smbus.org/specs/
0XAD IC DEVICE ID (BR)
The IC Device ID is a block readable register that reports the
device product name being addressed. The product ID that is
stored in the register is “ISL28025”. Each character is stored as
an ASCII number. A 0x30 equals ASCII “0”. A 0x49 translates to
an ASCII “I”. Figure 65 illustrates the convention for performing a
block read.
0XAE IC_DEVICE_REV (BR)
The IC Device Revision is a block readable register that reports
back the revision number of the silicon and the version of the
silicon. The register is 3 bytes in length.
TABLE 5. 0xAE IC DEVICE REV REGISTER DEFINITION
BIT NUMBER
D[23:12]
D[11]
D[10:0]
Bit Name
N/A
Silicon Version Silicon Revision
Default Value 0000 0011 0000
0
0000 0000 0010
SILICON VERSION D[11]
Data bit 11 of the IC Revision register reports the version of the
silicon.
TABLE 6. D[11] SILICON VERSION BIT DEFINED
D4
STATUS
0
60V
1
12V
Global IC Controls
0X12 RESET DEFAULT ALL (S)
The Restore Default All register is a send byte command that
restores all registers to the default state defined in Table 2 on
page 22.
0X01 OPERATION (R/W)
The Operation register is a read/writable byte register that
controls the overall power-up state of the chip. Data Bit 7 of the
register configures the power status of chip. The power status is
defined in Table 7. Yellow shading in the table is the default
setting of the bit at power-up.
TABLE 7. 0x01 OPERATION REGISTER BIT 7 DEFINED
D7
STATUS
0
Power-down
1
Normal Operation
Primary and Auxiliary Channel Controls
0XD2 SET DPM MODE (R/W)
The Set DPM Mode is a read/writable byte register that controls
the data acquisition behavior of the chip.
TABLE 8. 0xD2 SET DPM MODE REGISTER DEFINITION
BIT
NUMBER D[7]
D6
D[5] D[4]
D[3]
D[2:0]
Bit Name N/A
ADC
Enable
ADC
State
Post
Trigger
State
ADC
Mode
Type
Operating
Mode
Default 0
0
0
0
1
010
Value
ADC ENABLE D[6]
Data Bit 6 of the Set DPM Mode register controls the ADC power
state within the DPM chip. At power-up, the ADC is powered up
and is available to take data.
TABLE 9. 0xD2 SET DPM MODE REGISTER BIT 6 DEFINED
D6
ADC PD
0
Normal Mode
1
ADC Powered Down
ADC STATE D[5]
Data Bit 5 of the Set DPM Mode register controls the ADC state.
The idle state of the ADC does not acquire data from any input of
the DPM. Normal operating mode has the ADC acquiring data in
a systematic way.
TABLE 10. 0xD2 SET DPM MODE REGISTER BIT 5 DEFINED
D5
ADC STATE
0
Normal State
1
ADC in Idle State
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FN8388.3
June 17, 2015