ISL28025 Datasheet, PDF (30/47 Pages) Intersil Corporation – Precision Digital Power Monitor with Real Time Alerts

ISL28025
TABLE 23. Vbus_OV_OT_Set BITS DEFINED
Vbus_OV_OT_Set: D[5:0]
OV THRESHOLD
VALUE
OT THRESHOLD
VALUE
00 0000
25% of FS
-144
00 0001
(25 + 1.56)% of FS
-138.3
00 0010
(25 + 3.12)% of FS
-132.6
...............
....................
....................
11 1101
(125 to 4.68)% of FS
210
11 1110
(125 to 3.12)% of FS
215.7
11 1111
(125 to 1.56)% of FS
221.4
Table 23 defines an abbreviated breakdown to set the OV/OT
comparator level. The shaded row is the default condition.
0XDB VOUT UV THRESHOLD SET (R/W)
The V_OUT UV Threshold Set register is a read/writable byte
register that controls the threshold voltage level to the
undervoltage comparator. The description of the functionality
within this register is found in Table 24.
The compared reference voltage level to the UV comparator is
generated from a 6-bit DAC. The 6-bit DAC has 4 to 6 voltage
ranges that are determined by the Vbus_Thres_Rng bits in the
Vout OV Threshold Set register.
TABLE 24. 0xDB VOUT UV THRESHOLD SET REGISTER DEFINITION
BIT
NUMBER
D[7:6]
D[5:0]
Bit Name
N/A
Vbus_UV_Set
Default
00
Value
00 0000
VBUS_UV_SET D[4:0]
The Vbus_UV_Set bits control the undervoltage level to the input
of the UV comparator. The LSB of the DAC is 1.56% of the full
scale range chosen using the Vbus_Thres_Rng bits.
The undervoltage ranges from 0% to 100% of the full scale range
set by the Vbus_Thres_Rng bits.
TABLE 25. Vbus_UV_Set BITS DEFINED
Vbus_UV_Set: D[5:0]
UV THRESHOLD VALUE
00 0000
0%
00 0001
1.56% of FS
00 0010
3.12% of FS
...............
....................
11 1101
(100 to 4.68)% of FS
11 1110
(100 to 3.12)% of FS
11 1111
(100 to 1.56)% of FS
Table 25 defines an abbreviated breakdown to set the
undervoltage comparator levels. The shaded row is the default
condition.
0XDC I_OUT OC THRESHOLD SET (R/W)
The I_OUT OC Threshold Set register is a read/writable word
register that controls the threshold current level to the
overcurrent comparator. The description of the functionality
within this register is found in Table 26.
TABLE 26. 0xDC I_OUT OC THRESHOLD SET REGISTER DEFINITION
BIT
NUMBER D[15:10] D[9] D[8:7] D[6]
D[5:0]
Bit Name N/A
Iout_Dir N/A
Vshunt
Thres
Rng
Vshunt_OC_Set
Default 0000 00 0
00
0
Value
11 1111
The overcurrent threshold is defined through the V_SHUNT reading.
The product of the current through the shunt resistor defines the
V_SHUNT voltage to the DPM. The current through the shunt
resistor is directly proportional the V_SHUNT voltage measured by
the DPM. An overvoltage threshold for V_SHUNT is the same as an
overcurrent threshold.
IOUT_ DIR D[9]
The Iout_Dir bit controls the polarity of the V_SHUNT voltage
threshold. The bit functionality allows an overcurrent threshold to
be set for currents flowing from VINP to VINM and the reverse
direction. Table 27 defines the range settings for the V_BUS
threshold detector. The yellow shaded row denotes the default
setting.
TABLE 27. Vbus_Thres_Rng BITS DEFINED
Iout_Dir: D[9]
CURRENT
DIRECTION
0
VINP to VINM
1
VINM to VINP
VSHUNT_THRES_RNG D[6]
The Vshunt_Thres_Rng bit sets the overvoltage threshold range
for the overcurrent DAC. The selectable V_SHUNT range improves
the overvoltage threshold resolution for lower full scale current
applications. Table 28 defines the range settings for the V_BUS
threshold detector. The yellow shaded row denotes the default
setting.
TABLE 28. Vshunt_Thres_Rng BIT DEFINED
Vshunt_Thres_Rng: D[6]
V_SHUNT
(RANGE)
0
80mV
1
40mV
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FN8388.3
June 17, 2015