ISL28025 Datasheet, PDF (35/47 Pages) Intersil Corporation – Precision Digital Power Monitor with Real Time Alerts

ISL28025
0X1B SMBALERT MASK (BR/BW)
0XDF SMBALERT2 MASK (BR/BW)
The SMBALERT registers are block read/writable registers that
mask error conditions from electrically triggering the respective
SMBALERT pin.
The SMBALERT can mask bits of any of the status registers.
Masking lower level bits prevents the hierarchal bit from being
set. For example, a COMERR bit being masked will not set the
CML bit of the Status Byte register.
To mask a bit, the first data byte is the register address of the
bit(s) to be masked. The second and third data bytes are the
masking bits of the register. A masking bit of 1 prevents the
signal from triggering an interrupt.
All alert bits are masked as the default state for both the SMB
alert pins. The master needs to send instructions to unmask the
alert bits.
As an example, a user would like to allow the COMERR bit to
trigger a SMBALERT2 interrupt while masking the rest of the
alerts within the Status CML register. The command that is sent
from the master to the DPM is the slave address, SMBALERT2
register address, Status CML register address and the mask bit
value. In a hexadecimal format, the data sent to the DPM is as
follows; 0x80 DF 7E FD.
To read the mask status of any alert register, a four byte write
command, without PEC, consisting of the slave address of the
device, the SMB mask register address, the number of bytes to
be read back and the register address of the mask to be read.
Once the write command has commenced, a read command
consisting of the device slave address and the register address of
the SMB mask will return the mask of the desired alert register.
As an example, a user would like to read the status of the Status
Byte register. The first command sent to the DPM is in
hexadecimal bytes is 0x82 1B 01 78. The second command is a
standard read. The slave address is 0x83 (0x82 + read bit set)
and the register address is 0x1B.
SMBALERT1 RESPONSE ADDRESS
It is common that the SMBALERT1 pin of each ISL28025 device
is shared to a single GPIO pin of the microcontroller. The
SMBALERT1 pin is an open drain allowing for multiple devices to
be OR’ed to a single GPIO pin.
The SMBALERT1 Response Address command reports the slave
address of the device that has triggered alert. The SMB Respond
Address command is shown in Figure 69.
1
7
11
8
11
S
Alert Response
Address
Rd A Device Address
AP
1
1
7
11
8
1
8
11
S
Alert Response
Address
Rd
A Device Address A
PEC A P
1
FIGURE 69. THE COMMAND STRUCTURE OF THE SMBALERT
RESPONSE ADDRESS
The alert response address is 0x18. In the event of multiple
alerts pulling down the GPIO line, the alert respond command
will return the lowest slave address that is connected to the I²C
bus. Upon clearing the lowest slave address alert, the alert
command will return the lowest slave address of the remaining
alerts that are activated.
The alert response is operable when the interrupt active state is
forced low by the device at the SMBALERT1 pin. Changing
SMBALERT1 interrupt polarity or forcing an interrupt will enable
the alert response. By design the open drain of the SMBALERT1
pin allows for ANDing of the interrupt via a pull-up resistor. The
alert response command is valid for only the SMBALERT1 pin.
The alert response command will return a 0x19 when there are
no errors detected.
External Clock Control
The DPM has an external clock feature that allows the chip to be
synchronized to an external clock. The feature is useful in limiting
the number of clocks running asynchronously within a system.
0XE5 CONFIGURE EXTERNAL CLOCK (R/W)
The Configure External Clock register is a read/writable byte
register that controls the functionality of the external clock
feature.
TABLE 43. 0xE5 CONFIGURE EXTERNAL CLOCK REGISTER DEFINITION
BIT NUMBER D[7]
D[6]
D[5:4} D[3:0]
Bit Name ExtCLK_EN SMBLALERT2OEN N/A EXTClkDIV
Default
0
Value
0
00
0000
EXTCLK_EN D[7]
The ExtClk_EN bit enables the external clock feature. The
ExtClk_En default bit setting is 0 or disabled. A bit setting of 1
disables the internal oscillator of the DPM and connects circuitry
such that the system clock is routed from the external clock pin.
SMBALERT2_OEN D[6]
The SMBALERT2_OEN bit within the Configure External Clock
register either enables or disables the buffer that drives the
SMBALERT2 pin.
TABLE 44. SMBALERT2_OEN BIT DEFINED
SMBALERT_OEN
SMBALERT2 STATUS
0
Disabled
1
Enabled
EXTCLKDIV D[3:0]
The EXTCLKDIV bits control an internal clock divider that is useful
for fast system clocks. The internal clock frequency from pin to
chip is represented in Equation 13.
freq _internal
f _EXTCLK
(ClkDiv8)  8
(EQ. 13)
f_EXTCLK is the frequency of the signal driven to the External Clock
pin. ClkDiv is the decimal value of the clock divide bits.
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FN8388.3
June 17, 2015