ISL28025 Datasheet, PDF (37/47 Pages) Intersil Corporation – Precision Digital Power Monitor with Real Time Alerts

ISL28025
SMBus, PMBus Support
The ISL28025 supports SMBus and PMBus protocol, which is a
subset of the global I²C protocol. SMBCLK and SMBDAT have the
same pin functionality as the SCL and SDA pins, respectively. The
SMBus operates at 100kHz. The PMBus protocol standardizes
the functionality of each register by address.
Device Addressing
Following a start condition, the master must output a slave address
byte. The 7 MSBs are the device identifiers. The A0, A1 and A2 pins
control the bus address (these bits are shown in Table 45). There
are 55 possible combinations depending on the A0, A1 and A2
connections.
A2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I2CVCC
...............
I2CVCC
SDA
SDA
...............
SDA
SCL
...............
SCL
SCL
TABLE 45. I²C SLAVE ADDRESSES
A1
A0
GND
GND
GND
I2CVCC
GND
SDA
GND
SCL
I2CVCC
GND
I2CVCC
I2CVCC
I2CVCC
SDA
I2CVCC
SCL
SDA
GND
SDA
I2CVCC
SDA
SDA
SDA
SCL
SCL
GND
SCL
I2CVCC
SCL
SDA
SCL
SCL
GND
GND
..............
..............
SCL
SCL
GND
GND
GND
VCC
..............
..............
SCL
SCL
GND
GND
..............
..............
SDA
X
SCL
X
SLAVE ADDRESS
1000 000
1000 001
1000 010
1000 011
1000 100
1000 101
1000 110
1000 111
1001 000
1001 001
1001 010
1001 011
1001 100
1001 101
1001 110
1001 111
1010 000
..................
1011 111
1100 000
Do Not Use. Reserved
..................
1101 111
1110 000
..................
Do Not Use. Reserved
Do Not Use. Reserved
SIGNALS FROM THE
MASTER
SIGNAL AT SDA
SIGNALS FROM
THE ISL28025
S
WRITE
T
A ^{IDENTIFICATION}
R
BYTE
ADDRESS
BYTE
T
1nnnnnn0 0000
A
A
C
C
K
K
DATA
BYTE
A
C
K
DATA
BYTE
S
T
O
P
A
C
K
FIGURE 72. BYTE WRITE SEQUENCE (SLAVE ADDRESS INDICATED BY nnnn)
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FN8388.3
June 17, 2015