HC55120_06 Datasheet, PDF (19/36 Pages) Intersil Corporation – Low Power Universal SLIC Family

HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
Substituting Equation 21 for V_TR in Equation 30 and
simplifying results in Equation 31.
G_{4 – 4}
=
-^V----^T----^X--
V_RX
=
–2
⎛
⎜
⎝
Z_-Z---L-L---+_-+----2_-Z---R_{-T---R-P--⎠⎟⎞}
(EQ. 31)
(AC) 2-Wire Impedance
The AC 2-wire impedance (Z_TR) is the impedance looking
into the SLIC, including the fuse resistors. The formula to
calculate the proper Z_T for matching the 2-wire impedance is
shown in Equation 32.
Z_T = 200 • (Z_TR – 2R_P)
(EQ. 32)
Equation 32 can now be used to match the SLIC’s
impedance to any known line impedance (Z_TR).
EXAMPLE:
Calculate Z_T to make Z_TR = 600Ω in series with 2.16µF.
R_P = 30Ω.
Z_T
=
200
⎛
⎜
⎝
600
+
-----------------¹------------------
j ω 2.16 X 10^–6
–
(
2)
(
⎞
30)⎟
⎠
(EQ. 33)
Z_T = 108kΩ in series with 0.0108µF.
Note: Some impedance models, with a series capacitor, will
cause the op-amp feedback to behave as an open circuit
DC. A resistor with a value of about 10 times the reactance
of the Z_T capacitor (2.16µF/200 = 10.8nF) at the low
frequency of interest (200Hz for example) can be placed in
parallel with the capacitor in order to solve the problem
(736kΩ for a 10.8nF capacitor).
Calculating Tip and Ring Voltages
The on hook tip to ground voltage is calculated using
Equation 34. The minus 1.0 volt results from the SLIC self
programming. ISH- is the maximum loop current for a
constant on hook overhead voltage (ISH- = I_SHD(0.6)) and
the value of R_SAT(off) is calculated in Equation 4.
On hook Tip Voltage
V_TIP(onhook)
=
– 1.0V + –
(
I
S
H-
)
⎛
⎝
R_{-----S----A-2---T----o---f--f⎠⎞}
(EQ. 34)
The off hook tip to ground voltage is calculated using
Equation 35. I_LOOP(min) is the minimum loop current
allowed by the design and the value of R_SAT(off) is
calculated in Equation 4.
Off hook Tip Voltage
V_TIP(offhook)
=
–
1
V
–
(
I_L
O
OP
(m
i
n)⁾
-^R----^S----^A----^T---⁽---^o---^f--^f--⁾
2
– I_LOOP(MAX) × R_P
(EQ. 35)
The on hook ring to ground voltage is calculated using
Equation 36. The 1.5 volt results from the SLIC self
programming. ISH- is the maximum loop current for a
constant on hook overhead voltage (ISH- = I_SHD(0.6)) and
the value of R_SAT(off) is calculated in Equation 4.
On hook Ring Voltage
V_RING(onhook)
=
V_BH + 1.5V + (ISH
)
⎛
⎝
R_{-----S----A---2-T----(--o---f--f--)⎠⎞}
(EQ. 36)
The calculation of the ring voltage with respect to ground in
the off hook condition is dependent upon whether the SLIC
is in current limit or not.
The off hook ring to ground voltage (in current limit) is
calculated using Equation 37. I_LIM is the programmed loop
current limit and R_L is the load resistance across tip and ring.
The minus 0.2V is a correction factor for the 60kΩ slope in
Figure 15.
Off hook Ring Voltage in Current Limit
V_RING(CL) = V_TIP(offhook) – I_LOOP(MAX)R_L – 0.2V (EQ. 37)
The off hook ring to ground voltage (not in current limit) is
calculated using Equation 38. The 1.5V results from the
SLIC self programming. I_LOOP(min) is the minimum loop
current allowed by the design and the value of R_SAT(off) is
calculated in Equation 4.
Off hook Ring Voltage not in Current Limit
V_RING(NCL) = V_BH + 1.5V + (I_LOOP(min))⎝⎛-^R----^S----^A---₂-^T----⁽--^o---^f--^f--⁾_⎠⎞
–I_LOOP(MIN) × R_P
(EQ. 38)
Layout Considerations
Systems with Dual Supplies (V_BH and V_BL)
If the V_BL supply is not derived from the V_BH supply, it is
recommended that an additional diode be placed in series
with the V_BH supply. The orientation of this diode is anode
on pin 8 of the device and cathode to the external supply.
This external diode will inhibit large currents and potential
damage to the SLIC, in the event the V_BH supply is shorted
to GND. If V_BL is derived from V_BH then this diode is not
required. Suggested (not required) supply sequence V_BH -
V_BL- V_CC.
Floating the PTG Pin
The PTG pin is a high impedance pin (500kΩ) that is used to
program the 2-wire to 4-wire gain to either 0dB or -6dB.
If 0dB is required, it is necessary to float the PTG pin. The
PC board interconnect should be as short as possible to
minimize stray capacitance on this pin. Stray capacitance on
this pin forms a low pass filter and will cause the 2-wire to
4-wire gain to roll off at the higher frequencies.
If a 2-wire to 4-wire gain of -6dB is required, the PTG pin
should be grounded as close to the device as possible.
19
FN4659.13
June 1, 2006