ISL6592 Datasheet, PDF (18/21 Pages) Intersil Corporation – 6-Phase Digital Multiphase Controller

ISL6592
as the current increases. Both of these mechanisms allow
hiccup mode overcurrent protection, where the controller
continues to try to provide a regulated output voltage while in
overcurrent. Alternatively, a threshold can be set where the
overcurrent condition will cause the controller to initiate
shutdown.
Over-Temperature Alert/Shutdown: Both the internal and
external temperature monitors are able to provide fault
telemetry in order to shut down the VR in an over-
temperature condition. Two programmable thresholds are
available for temperature faults. Crossing of the first
threshold can be used to only generate a fault report.
Crossing the second threshold can be used to cause a
shutdown to occur.
CRC Failure: The integrity of loading the configuration from
the NVM to the controller's registers is checked through a
cyclic redundancy code (CRC) check of the data contents. A
CRC failure prevents the controller from leaving the inactive
state.
Calibration Failure: Calibration failures can be detected as
either out of range parameter computations or inability to
achieve a regulation target in the given time-frame. These
failures typically indicate a component is damaged or
missing.
I²C Interface
All operating parameters in the ISL6592 is configurable via
the I²C interface. Status can also be read back via the same
interface. The ISL6592 operates as a slave at a standard
speed of 100kHz.
Three transactions are supported on the I²C interface: 1) Set
current address, 2) Write register, 3) Read register from
current address.
All transactions start with a control byte sent from the I²C
master device. The control byte begins with a Start condition,
followed by 7-bits of slave address. The last bit sent by the
master is the R/W bit and is 0 for a write. If any slaves on the
I²C bus recognize their address, they will Acknowledge by
pulling the serial data line low for the last clock cycle in the
control byte. If no slaves exist at that address or are not
ready to communicate, the data line will be 1, indicating a
Not Acknowledge condition. The ISL6592 address on the
I²C bus is 1110_000 or 1110_001, with the LSB set by the
input pin SADDR.
To write a register in the ISL6592, the master sends a control
byte with the R/W bit set to 0, indicating a write. If it receives
an Acknowledge from the ISL6592, it sends a byte
representing the address MSB. The ISL6592 will respond
with an Acknowledge. The master then sends a byte
representing the address LSB. The ISL6592 will respond
with an Acknowledge. The master then sends a byte
representing the data MS-byte to be written at the current
address. The ISL6592 will respond with an Acknowledge.
The master then sends a byte representing the data LS-byte
to be written at the current address. The ISL6592 will
respond with an Acknowledge. The master then issues a
Stop condition, indicating to the ISL6592 that the current
transaction is complete.
To set the current 16-bit address in the ISL6592, the master
sends a control byte with the R/W bit set to 0, indicating a
write. If it receives an Acknowledge from the ISL6592, it
sends a byte representing the address MS-byte. The
ISL6592 will respond with an Acknowledge. The master then
sends a byte representing the address LS-byte. The
ISL6592 will respond with an Acknowledge. The master then
issues a Stop condition, indicating to the ISL6592 that the
current transaction is complete. Any read commands issued
to the ISL6592 will return data from this address.
To read a register from the ISL6592, the master first sets the
address to read from. It then sends a control byte with the
R/W bit set to 1, indicating a read. If it receives an
Acknowledge from the ISL6592 it sends 8 clocks but does
not drive the serial data line. The ISL6592 will respond with
the MS-byte at the current address. The master will respond
with an Acknowledge to indicate to the ISL6592 that the
transaction is not yet complete. The master again sends 8
clocks but does not drive the serial data line. The ISL6592
will respond with the LS-byte at the current address. The
master will respond with a Not Acknowledge to indicate to
the ISL6592 that the transaction is complete. The ISL6592
will stop driving the serial data line. The master then issues a
Stop condition to indicate that the transaction is complete.
If the ISL6592 has started an internal operation in response
to a transaction on the I²C bus (register read/write, flash
write, flash page erase) but the operation has not completed
before the last Acknowledge slot in the I²C bus protocol, the
ISL6592 will add wait states by stretching the low portion of
the last clock cycle. This also occurs in response to
read/write requests to addresses that do not support
physical memory in the ISL6592. In this case, the ISL6592
will add wait states until an internal watchdog timer expires,
and the I²C bus is guaranteed to be released.
18
FN9163.1
August 5, 2005