ISL6592 Datasheet, PDF (13/21 Pages) Intersil Corporation – 6-Phase Digital Multiphase Controller

ISL6592
The current in the power stage can then be inferred from the
current ADC measurement if the drain-source resistance
(r_DS(ON)) of the FET is known. The r_DS(ON) of each FET
can be either programmed as a default value, or it can be
determined by running the calibration routine either one time
at system test or every time the system starts up. Calibration
is performed by providing a known current load while the
regulator is on and correcting the gain and offset of the
current measurement. This requires the use of a precision
external current source consisting of a dedicated calibration
FET and sense resistor. The ISL6592 senses the voltage
across the resistor and provide a variable voltage to drive
the gate of the calibration FET, varying its r_DS(ON) such that
the current through the FET and resistor are under closed
loop control. The calibration current and voltage level at
which calibration occurs are programmable, and the
calibration routine can be bypassed if the default values are
to be used. The r_DS(ON) value is compensated for
temperature drift using either the on-chip temperature sense
or an external thermistor that can be placed close to the
power stage.
The external temperature sense input, TEMP_SEN, is a
virtual ground input with a fixed offset of 150mV. An external
negative TC thermistor is tied to ground, generating the input
current for the measurement. Series resistors or shunt
resistors can be used to scale the current. The current range
is the same as the current sense inputs, from 0 to 275µA in
4.3µA steps. Default values should be chosen such that the
ADC range is not clipped. The ADC measurements are
converted to temperature using a programmable 4-segment
piece-wise linear table. The internal proportional-to-absolute
temperature (PTAT) reference is digitized directly, using a
linear curve fit. Both internal and external temperature
measurements are multiplexed through the current ADC at a
low frequency, providing run-time internal and external
temperature information to perform temperature
compensation, reporting, alerts, and shutdown.
When used with the ISL6597 integrated power stage, the
integrated current sense output can be directly interfaced
with the ISL6592 current sense input. The integrated current
sense provides superior accuracy, with loadline accuracy
comparable to those achieved with series sense resistors.
Additionally, the integrated temperature sense in the
ISL6597 can be used instead of the external thermistor,
providing direct power stage measurements to the system.
Digital Control Loop and PWM Generation
The digital control loop uses a proportional, integral, and
derivative (PID) compensator to drive the digitized sense
voltage to the desired target. An additional second derivative
gain term and a 2nd order post-filter provide additional high
order zeros and poles to further refine the wideband
characteristics of the loop. All loop parameters are
programmable over a wide range of values, allowing loop
bandwidths of 10-300kHz to be attained depending on the
number and type of power stages used.
The effective transfer function of the compensator is given
by:
H(z)
=



1^{-----–--K---}z^{-i--–---1-}
+
K_p
+
K_d(
1
–
z^–1)
+
K_d2(
1
–
z^–1)²ï£·ï£¶




1^{-----+-----1K-----}_f^+-_d^----K₁^---z^{-f--d–---11-----++----KK-----ff--dd---22---}z^{---–---2--}



-_N----_p---_h---^K--_â‹--^m-_d----^o_i-_v--^d--_{_}---_s---_e---_{l}


V_{---Q--i-n--}
where:
Ki, Kp, Kd, and Kd2 are the integral, proportional,
derivative, and second derivative gain terms
Kfd1 and Kfd2 are the coefficients of a second order all
pole low pass post-filter
Kmod is a programmable maximum duty cycle scaling
term
Nph is the number of phases and div_sel is the divider
ratio setting the switching frequency
Vin is the power stage input voltage, typically 12V
Q is the ADC step size, 3.125mV
The control loop operates at the same frequency as the
voltage ADC, which is synchronous to the switching
frequency and given by:
Fs = 2 * Nph * Fsw = 156.25MHz/div_sel
The compensator digital output is converted to a pulse width
using a digital counter based pulse width modulator. The
pulse width modulator uses 2 successive samples to
modulate the leading edge and then the trailing edge of a
pulse. The modulator provides for monotonic edge
placements with a resolution of 100ps. The next 2 samples
are then used to modulate the next phase in the firing
sequence. The pulse width modulator is capable of setting a
maximum duty cycle limit, overlapping adjacent phases, a
minimum pulse width of 13ns, and also producing zero pulse
width with minimal glitching.
Voltage Identification Codes
The target voltage is provided by external parallel 6-bit
voltage identification (VID) inputs. The VID maps can be
configured as either Intel® VID, AMD®, or programmable
offset tables. The ISL6592 is fully compliant with VRD/VRM
10.1 and 10.2 deglitching and dynamic VID stepping
requirements.
13
FN9163.1
August 5, 2005