ISL6592 Datasheet, PDF (11/21 Pages) Intersil Corporation – 6-Phase Digital Multiphase Controller

ISL6592
over the serial bus to identify the specific fault event. Fault
detection includes the following:
• Input Undervoltage
• Output Overvoltage
• Output Undervoltage
• High-side Short
• Per Phase Overcurrent
• Total Output Overcurrent
• Two levels of Internal Temperature Protection
• Two levels of External Temperature Protection
• Configuration Failure
• Calibration Range Failure
• Calibration Time-out Failure
The ISL6592 is also optimized for use with the ISL6597
integrated power stage to deliver a high performance VR
solution. The ISL6597 offers the following benefits when
combined with the ISL6592 controller:
• Low delay, fast transition, low r_DS(ON) (13mΩ) integrated
high side P-channel FET
• Low delay, high drive (2A) low side N-channel FET driver
• High accuracy, low drift integrated current mirror, allowing
lossless current sensing with loadline accuracy
comparable to series sense resistor solutions
• Power supply sequence independence between the
power input (12V), low side driver supply (5-12V), and
controller supply (3.3V)
• Direct high side short detect and crowbar capability,
operates off the 12V input supply and is thus independent
of controller power supply
Please see the ISL6597 data sheet for more details on the
performance, capability, and interface requirements of
ISL6592/ISL6597 systems.
Theory of Operation
Power Up and Initialization
The ISL6592 is designed to provide supply sequence
independence and graceful turn-on and turn-off operation. It
operates from a single +3.3V supply, while an on-chip low
drop-out (LDO) regulator generates an internal +2.5V
supply. Power-up controller configuration is initialized by
either an internal threshold based power-on reset, or by an
external reset pin (RST_N). During controller configuration,
the contents of the NVM are read into the controller's
registers. During configuration, all outputs are three-stated,
allowing board pull-up or pull-down resistors to set the
correct default level.
Once configuration is completed, the controller enters an
inactive state. Outputs assume their default values, which
may be low, high or three-state. During the inactive state, the
controller can communicate over the serial bus, report
configuration or inactive state faults (e.g. high side short).
The controller will leave the inactive state and begin soft-
start once it has a valid VID, OEN is asserted, and the 12V
power input is valid. The 12V input is sensed through a
resistive divider on the board, and a programmable
threshold comparator must be tripped if the input
undervoltage lockout is enabled. The sense circuit can be
easily modified to also sense an independent or sequenced
lower drive voltage typically used to optimize the efficiency of
the power stage low side FET.
Soft-Start and Calibration
Prior to entering an active regulating state, the ISL6592
performs a well-controlled, monotonic initial ramp or "soft-
start". Soft-start is performed by actively regulating the load
voltage while digitally ramping the target voltage from 0 to
the voltage set. During this time, the optional power-up
system calibration can be performed. The calibration
algorithm compensates for variations in low-side FET
r_DS(ON), parasitic inductance and resistance by regulating to
a low voltage level, putting a known current load through
each phase individually and compensating for the current
sense gain and offset error, as well as changes in
temperature. Alternatively, default compensation values can
be used, or the compensation values can be computed
during system test and stored in memory. The external
current load needed to perform calibration can be
implemented with a precision resistor and N-channel FET.
The voltage across the resistor is sensed and the N-channel
FET gate voltage is adjusted through an internal opamp loop
to provide the desired precision current. The calibration
current level and the voltage level at which the calibration is
performed are both programmable.
After the soft-start ramp is completed, the processor's
leakage current is measured. At this point the regulator
enters the active regulation state and the VCC_PWRGD pin
transitions from "0" to "1," indicating that the microprocessor
voltage is within 90% of the target value.
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FN9163.1
August 5, 2005