ISL6592 Datasheet, PDF (17/21 Pages) Intersil Corporation – 6-Phase Digital Multiphase Controller

ISL6592
Output Firing Sequence
The PWM output and current sense (ISEN) pins of the
ISL6592 have been assigned such they can be placed
sequentially for PC board layouts (i.e. phase 2 next to 1, phase
3 next to 2, etc...). The output phases are set in a pre-wired
firing order to facilitate layout of high phase count systems.
For high phase count systems, the VRD layout in the
motherboard will likely require the power components to be
laid out across two sides of the processor. The firing
sequence shown in the table below ensures that for a highly
distributed power array, the maximum spatial distribution can
be obtained between sequential phases.
TABLE 4. OUTPUT FIRING SEQUENCE
φ
FIRING SEQUENCE
2 1 Æ 2 Æ 1 Æ 2 Æ 1 Æ 2 Æ 1 Æ 2 Æ 1 Æ 2 Æ 1 Æ 2 ...
3 1 Æ 2 Æ 3 Æ 1 Æ 2 Æ 3 Æ 1 Æ 2 Æ 3 Æ 1 Æ 2 Æ 3 ...
4 1 Æ 4 Æ 2 Æ 3 Æ 1 Æ 4 Æ 2 Æ 3 Æ 1 Æ 4 Æ 2 Æ 3 ...
5 1 Æ 4 Æ 2 Æ 5 Æ 3 Æ 1 Æ 4 Æ 2 Æ 5 Æ 3 Æ 1 Æ 4 ...
6 1 Æ 4 Æ 2 Æ 5 Æ 3 Æ 6 Æ 1 Æ 4 Æ 2 Æ 5 Æ 3 Æ 6 ...
Fault Detection and Fault Handling
The ISL6592 provides a very flexible fault detection reporting
and handling mechanism. Fault detection capability
includes:
• Input Undervoltage Protection (IUVP)
• Output Overvoltage Protection (OOVP)
• Output Undervoltage Protection (OUVP)
• High-side Short (HSS)
• Per Phase Overcurrent Protection (OCP)
• Total Output Overcurrent
• Two levels of Internal Temperature Protection
• Two levels of External Temperature Protection
• Configuration Failure
• Calibration Range Failure
• Calibration Time-out Failure
All individual faults are latched and reported over the serial
interface. Two configurable fault outputs are provided. Each
output allows independent masking of all faults, allowing a
subset of faults to be reported over that pin. The outputs can
also be configured as either latched or unlatched, active high
or active low polarity, and CMOS or open drain outputs.
Typical usage of the configurable fault pins would be as a
crowbar signal to drive an external crowbar device,
temperature alert to notify the system a thermal shutdown is
imminent, or as an interrupt to cause a micro-controller to
poll the fault registers.
Shutdown operation also allows a subset of faults to be
individually masked. Additionally, the shutdown recovery can
be either autonomous or latched. For autonomous recovery,
the faults are not latched, so if the fault condition is
eliminated when the controller returns to an inactive state, it
will wait for a programmable time period, and then attempt a
new soft-start. If the fault condition reoccurs, the controller
will recommence the shutdown sequence, continuing this
cycle indefinitely until the fault condition is eliminated. The
programmable delay ensures a sufficiently low duty cycle to
prevent the regulator components from being damaged from
power cycling, assuming the fault condition itself is not
immediately destructive.
For latched shutdown, user intervention to clear the latched
fault is required before a new soft-start can be attempted.
User intervention must come in the form of OUTEN toggle,
RESET_N toggle, or controller power cycle.
In addition to fault reporting, there are additional fault
handling capabilities specific to each fault type that attempts
to provide more graceful fault handling than a shutdown, but
more active than simply reporting. The specific fault
detection capability and alternate fault handling capability is
as follows:
IUVP: The V12_SEN input continuously senses the +12V
supply through a nominally 10:1 resistive divider. A
comparator with a programmable threshold is used to
indicate an undervoltage condition. IUVP can be used to
independently provide either an undervoltage lockout prior to
soft-start, or to both provide a lockout and force a shutdown
during active regulation.
OOVP/OUVP: Programmable comparators continuously
monitor the VSEN inputs to detect an output overvoltage or
undervoltage condition. The voltage threshold is set relative
to VID. OOVP is enabled during soft-start and active
regulation, while OUVP is enabled only during active
regulation.
HSS: The HSS (high-side short) comparator monitors the
power stages switch node through the ISEN inputs during
the inactive state. If a voltage above 1.0V is detected, the
comparator will indicate a HSS detect. If enabled, this will
turn all the low side FETs on and prevent the controller from
beginning the start-up process. The HSS comparators are
disabled in soft-start and active regulation.
OCP: The OCP (overcurrent protection) continuously
monitors all channel currents to determine whether any of
the currents are greater than a programmable threshold.
Two mechanisms work independently to control overcurrent
conditions. A cycle-by-cycle current limit operates by
disabling a channel for one cycle when its current exceeds
the threshold. A second mechanism monitors the average
current for an overcurrent condition. A programmable
threshold sets a current limit at which a steeper loadline is
implemented, quickly reducing the output voltage downward
17
FN9163.1
August 5, 2005