ISL6592 Datasheet, PDF (12/21 Pages) Intersil Corporation – 6-Phase Digital Multiphase Controller

ISL6592
FIGURE 3. SOFT-START/CALIBRATION SEQUENCE
(3-PHASE)
Shutdown
The ISL6592 also performs a controlled shutdown response
to minimize any voltage undershoot. The shutdown state can
be entered from the soft-start or active regulation states
either through user intervention (de-asserting OEN or all
one's VID), or through a detected fault such as over-
temperature or output overvoltage. During shutdown, the
PWM width is reduced at a steady programmable rate, and
then the power stage is three-stated once the pulse width
reaches 0.
After shutdown is complete, the controller re-enters the
inactive state after a fixed delay. This delay minimizes the
duty cycle associated with autonomous restarts if the fault
that caused the shutdown disappears once the output is
disabled. Alternatively, the fault can be configured so that it
is latched and clearing requires user intervention such as
toggling OEN, toggling RESET_N, or cycling power.
Switching Frequency
Timing is provided by an on-chip, factory trimmed,
temperature compensated oscillator. Additionally, this on-
chip oscillator can be frequency modulated by a pseudo
random pattern to spread the clock spectrum and reduce
system electro-magnetic interference (EMI).
The ISL6592 operates with a fixed switching frequency (i.e.
the switching frequency is fixed independent of load) that is
configurable between 300kHz and 1.5MHz. A programmable
divider is used to generate the switching frequency, where
the frequency is given by:
Fsw = 156.25MHz/(2 x div_sel x Nph)
where Fsw is the switching frequency, 156.25MHz is the
nominal frequency of the timing reference oscillator, div_sel
is the programmable divider ratio between 6 and 127, and
Nph is the number of phases between 2 and 6.
Although switching frequencies of less than 300kHz and
greater than 1.5MHz can be generated, various system
optimization parameters may not have adequate range to
optimize the loop outside this range.
Output Voltage Sensing and Voltage ADC
The ISL6592 is built around a high performance digital
feedback control loop that senses the differential voltage at
the load. This is used to generate the appropriate pulse
width modulated (PWM) waveforms to drive the power
stages and regulate the load voltage.
The differential sense voltage is digitized with a high speed,
high precision analog-to-digital converter (ADC). The on-
chip factory trimmed temperature compensated bandgap
voltage reference ensures the ADC accuracy is well within
the regulator setpoint accuracy requirements. The ADC is
sampled synchronously so that there are 2 ADC samples
per phase per switching cycle, at a frequency given by:
Fs = 156.25MHz/div_sel
The ADC also includes a post-filter which, when enabled,
provides a null at Fsw * (Nph/2), which is the ripple
frequency. This ripple null filter works in conjunction with an
internal analog anti-alias filter. The anti-alias filter is a single
pole, 2MHz low pass filter. The corner frequency can be
lowered by adding series resistors in the board.
Current Sensing and Current ADC
The ISL6592 provides for precise current monitoring in each
power stage, allowing for industry-leading loadline accuracy
for active voltage positioning (AVP). The current in each
power stage is sensed by measuring the voltage across the
bottom side FET in the middle of its on cycle. This voltage is
digitized using a multiplexed current ADC.
The current sense inputs (ISEN1 to ISEN6) are held at a
virtual ground with programmable offset from 25mV to
200mV. The large voltage swing at the drain of the low side
FET is eliminated by using a series resistor, converting the
signal to a current equal to:
Isense = (Voff - Vds)/Rsense
where Isense is the current sourced by the sense input, Voff
is the programmable offset, Vds is the voltage across the low
side FET, and Rsense is an external resistor whose value is
chosen to scale the input depending on the expected
r_DS(ON).
The input current is mirrored and multiplexed, then digitized
by the 6 bit current ADC with an effective input range of 0 to
275µA in 4.3µA steps. The ADC samples the current in each
phase once per switching cycle, and the sampling instant
can be varied using a programmable delay, such that
sampling in the middle of the ON cycle can be guaranteed.
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FN9163.1
August 5, 2005